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Efficient pattern for store truncate. Patch by Evandro Menezes. 

llvm-svn: 151166
This commit is contained in:
Sirish Pande 2012-02-22 16:45:10 +00:00
parent 53e191e77e
commit 2a783d5b94
4 changed files with 7 additions and 22 deletions
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13
llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
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@ -374,19 +374,6 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
O << "}"; O << "}";
} }
printInstruction(MI, O); printInstruction(MI, O);
} else if (MI->getOpcode() == Hexagon::STriwt) {
//
// Handle truncated store on Hexagon.
//
O << "\tmemw(";
printHexagonMEMriOperand(MI, 0, O);
O << ") = ";
unsigned SubRegNum =
TM.getRegisterInfo()->getSubReg(MI->getOperand(2)
.getReg(), Hexagon::subreg_loreg);
const char *SubRegName = getRegisterName(SubRegNum);
O << SubRegName << '\n';
} else if (MI->getOpcode() == Hexagon::MPYI_rin) { } else if (MI->getOpcode() == Hexagon::MPYI_rin) {
// Handle multipy with -ve constant on Hexagon: // Handle multipy with -ve constant on Hexagon:
// "$dst =- mpyi($src1, #$src2)" // "$dst =- mpyi($src1, #$src2)"

1
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -1397,7 +1397,6 @@ isValidOffset(const int Opcode, const int Offset) const {
case Hexagon::LDriw: case Hexagon::LDriw:
case Hexagon::STriw: case Hexagon::STriw:
case Hexagon::STriwt:
assert((Offset % 4 == 0) && "Offset has incorrect alignment"); assert((Offset % 4 == 0) && "Offset has incorrect alignment");
return (Offset >= Hexagon_MEMW_OFFSET_MIN) && return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
(Offset <= Hexagon_MEMW_OFFSET_MAX); (Offset <= Hexagon_MEMW_OFFSET_MAX);

12
llvm/lib/Target/Hexagon/HexagonInstrInfo.td
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@ -1999,11 +1999,6 @@ def STriw_indexed : STInst<(outs),
"memw($src1+#$src2) = $src3", "memw($src1+#$src2) = $src3",
[(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>; [(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>;
def STriwt : STInst<(outs),
(ins MEMri:$addr, DoubleRegs:$src1),
"memw($addr) = $src1",
[(truncstorei32 DoubleRegs:$src1, ADDRriS11_2:$addr)]>;
let mayStore = 1, neverHasSideEffects = 1 in let mayStore = 1, neverHasSideEffects = 1 in
def STriw_GP : STInst<(outs), def STriw_GP : STInst<(outs),
(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
@ -2745,7 +2740,7 @@ def : Pat<(i32 (trunc DoubleRegs:$src)),
def : Pat<(i1 (trunc DoubleRegs:$src)), def : Pat<(i1 (trunc DoubleRegs:$src)),
(i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>; (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>;
// Map memw(Rs) = Rdd -> memw(Rs) = Rt. // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr), def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr),
(STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src, (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
subreg_loreg)))>; subreg_loreg)))>;
@ -2755,6 +2750,11 @@ def : Pat<(truncstorei16 DoubleRegs:$src, ADDRriS11_0:$addr),
(STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src, (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
subreg_loreg)))>; subreg_loreg)))>;
// Map memw(Rs) = Rdd -> memw(Rs) = Rt.
def : Pat<(truncstorei32 DoubleRegs:$src, ADDRriS11_0:$addr),
(STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
subreg_loreg)))>;
// Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0. // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
def : Pat<(store (i1 -1), ADDRriS11_2:$addr), def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
(STrib ADDRriS11_2:$addr, (TFRI 1))>; (STrib ADDRriS11_2:$addr, (TFRI 1))>;

3
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
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@ -206,8 +206,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} else if ((MI.getOpcode() == Hexagon::STriw) || } else if ((MI.getOpcode() == Hexagon::STriw) ||
(MI.getOpcode() == Hexagon::STrid) || (MI.getOpcode() == Hexagon::STrid) ||
(MI.getOpcode() == Hexagon::STrih) || (MI.getOpcode() == Hexagon::STrih) ||
(MI.getOpcode() == Hexagon::STrib) || (MI.getOpcode() == Hexagon::STrib)) {
(MI.getOpcode() == Hexagon::STriwt)) {
// For stores, we need a reserved register. Change // For stores, we need a reserved register. Change
// memw(r30 + #10000) = r0 to: // memw(r30 + #10000) = r0 to:
// //