forked from OSchip/llvm-project
[DAG] combine assertsexts around a trunc
This was a suggested follow-up to: D37017 / https://reviews.llvm.org/rL313577 llvm-svn: 315206
This commit is contained in:
Sanjay Patel
parent
24ca39ce71
commit
2a61a821a0
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@ -328,7 +328,7 @@ namespace {
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SDValue visitSIGN_EXTEND(SDNode *N);
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SDValue visitZERO_EXTEND(SDNode *N);
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SDValue visitANY_EXTEND(SDNode *N);
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SDValue visitAssertZext(SDNode *N);
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SDValue visitAssertExt(SDNode *N);
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SDValue visitSIGN_EXTEND_INREG(SDNode *N);
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SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
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SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
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@ -1553,7 +1553,8 @@ SDValue DAGCombiner::visit(SDNode *N) {
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case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
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case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
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case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
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case ISD::AssertZext: return visitAssertZext(N);
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case ISD::AssertSext:
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case ISD::AssertZext: return visitAssertExt(N);
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case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
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case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
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case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
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@ -7978,20 +7979,19 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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return SDValue();
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}
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// TODO: These transforms should work with AssertSext too.
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// Change the function name, comments, opcode references, and caller.
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SDValue DAGCombiner::visitAssertZext(SDNode *N) {
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SDValue DAGCombiner::visitAssertExt(SDNode *N) {
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unsigned Opcode = N->getOpcode();
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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EVT AssertVT = cast<VTSDNode>(N1)->getVT();
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// fold (assertzext (assertzext x, vt), vt) -> (assertzext x, vt)
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if (N0.getOpcode() == ISD::AssertZext &&
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// fold (assert?ext (assert?ext x, vt), vt) -> (assert?ext x, vt)
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if (N0.getOpcode() == Opcode &&
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AssertVT == cast<VTSDNode>(N0.getOperand(1))->getVT())
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return N0;
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if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
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N0.getOperand(0).getOpcode() == ISD::AssertZext) {
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N0.getOperand(0).getOpcode() == Opcode) {
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// We have an assert, truncate, assert sandwich. Make one stronger assert
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// by asserting on the smallest asserted type to the larger source type.
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// This eliminates the later assert:
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@ -8000,13 +8000,13 @@ SDValue DAGCombiner::visitAssertZext(SDNode *N) {
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SDValue BigA = N0.getOperand(0);
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EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT();
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assert(BigA_AssertVT.bitsLE(N0.getValueType()) &&
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"Asserting zero/sign-extended bits from a type larger than the "
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"Asserting zero/sign-extended bits to a type larger than the "
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"truncated destination does not provide information");
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SDLoc DL(N);
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EVT MinAssertVT = AssertVT.bitsLT(BigA_AssertVT) ? AssertVT : BigA_AssertVT;
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SDValue MinAssertVTVal = DAG.getValueType(MinAssertVT);
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SDValue NewAssert = DAG.getNode(ISD::AssertZext, DL, BigA.getValueType(),
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SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(),
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BigA.getOperand(0), MinAssertVTVal);
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return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewAssert);
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}
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@ -37,10 +37,12 @@ entry:
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; GP32: and $2, $4, $5
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; GP64: and $2, $4, $5
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; GP64: and $1, $4, $5
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; MM: and16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: and16 $[[T0:[0-9]+]], $5
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; MM32: move $2, $[[T0]]
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; MM64: and $1, $4, $5
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%r = and i1 %a, %b
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ret i1 %r
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@ -52,10 +54,12 @@ entry:
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; GP32: and $2, $4, $5
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; GP64: and $2, $4, $5
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; GP64: and $1, $4, $5
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; MM: and16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: and16 $[[T0:[0-9]+]], $5
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; MM32: move $2, $[[T0]]
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; MM64: and $1, $4, $5
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%r = and i8 %a, %b
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ret i8 %r
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@ -67,10 +71,12 @@ entry:
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; GP32: and $2, $4, $5
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; GP64: and $2, $4, $5
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; GP64: and $1, $4, $5
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; MM: and16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: and16 $[[T0:[0-9]+]], $5
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; MM32 move $2, $[[T0]]
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; MM64: and $1, $4, $5
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%r = and i16 %a, %b
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ret i16 %r
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@ -135,7 +135,10 @@ define signext i1 @nor_i1(i1 signext %a, i1 signext %b) {
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entry:
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; ALL-LABEL: nor_i1:
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; ALL: nor $2, $5, $4
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; GP32: nor $2, $5, $4
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; GP64: or $1, $5, $4
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; MM32: nor $2, $5, $4
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; MM64: or $1, $5, $4
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%or = or i1 %b, %a
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%r = xor i1 %or, -1
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@ -146,7 +149,10 @@ define signext i8 @nor_i8(i8 signext %a, i8 signext %b) {
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entry:
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; ALL-LABEL: nor_i8:
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; ALL: nor $2, $5, $4
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; GP32: nor $2, $5, $4
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; GP64: or $1, $5, $4
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; MM32: nor $2, $5, $4
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; MM64: or $1, $5, $4
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%or = or i8 %b, %a
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%r = xor i8 %or, -1
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@ -157,7 +163,10 @@ define signext i16 @nor_i16(i16 signext %a, i16 signext %b) {
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entry:
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; ALL-LABEL: nor_i16:
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; ALL: nor $2, $5, $4
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; GP32: nor $2, $5, $4
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; GP64: or $1, $5, $4
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; MM32: nor $2, $5, $4
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; MM64: or $1, $5, $4
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%or = or i16 %b, %a
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%r = xor i16 %or, -1
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@ -24,10 +24,12 @@ entry:
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; GP32: or $2, $4, $5
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; GP64: or $2, $4, $5
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; GP64: or $1, $4, $5
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; MM: or16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: or16 $[[T0:[0-9]+]], $5
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; MM32 move $2, $[[T0]]
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; MM64: or $1, $4, $5
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%r = or i1 %a, %b
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ret i1 %r
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@ -39,10 +41,12 @@ entry:
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; GP32: or $2, $4, $5
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; GP64: or $2, $4, $5
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; GP64: or $1, $4, $5
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; MM: or16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: or16 $[[T0:[0-9]+]], $5
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; MM32 move $2, $[[T0]]
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; MM64: or $1, $4, $5
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%r = or i8 %a, %b
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ret i8 %r
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@ -54,10 +58,12 @@ entry:
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; GP32: or $2, $4, $5
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; GP64: or $2, $4, $5
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; GP64: or $1, $4, $5
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; MM: or16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: or16 $[[T0:[0-9]+]], $5
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; MM32 move $2, $[[T0]]
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; MM64: or $1, $4, $5
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%r = or i16 %a, %b
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ret i16 %r
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@ -35,10 +35,12 @@ entry:
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; GP32: xor $2, $4, $5
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; GP64: xor $2, $4, $5
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; GP64: xor $1, $4, $5
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; MM: xor16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: xor16 $[[T0:[0-9]+]], $5
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; MM32: move $2, $[[T0]]
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; MM64: xor $1, $4, $5
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%r = xor i1 %a, %b
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ret i1 %r
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@ -50,10 +52,12 @@ entry:
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; GP32: xor $2, $4, $5
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; GP64: xor $2, $4, $5
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; GP64: xor $1, $4, $5
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; MM: xor16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: xor16 $[[T0:[0-9]+]], $5
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; MM32: move $2, $[[T0]]
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; MM64: xor $1, $4, $5
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%r = xor i8 %a, %b
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ret i8 %r
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@ -65,10 +69,12 @@ entry:
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; GP32: xor $2, $4, $5
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; GP64: xor $2, $4, $5
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; GP64: xor $1, $4, $5
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; MM: xor16 $[[T0:[0-9]+]], $5
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; MM: move $2, $[[T0]]
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; MM32: xor16 $[[T0:[0-9]+]], $5
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; MM32: move $2, $[[T0]]
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; MM64: xor $1, $4, $5
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%r = xor i16 %a, %b
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ret i16 %r
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@ -62,8 +62,8 @@ define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
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define i32 @select_1_or_0_signext(i1 signext %cond) {
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; CHECK-LABEL: select_1_or_0_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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@ -95,9 +95,8 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
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define i32 @select_0_or_neg1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_0_or_neg1_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: notl %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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@ -129,7 +128,7 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
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define i32 @select_neg1_or_0_signext(i1 signext %cond) {
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; CHECK-LABEL: select_neg1_or_0_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsbl %dil, %eax
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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@ -161,9 +160,8 @@ define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
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define i32 @select_Cplus1_C_signext(i1 signext %cond) {
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; CHECK-LABEL: select_Cplus1_C_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: addl $41, %eax
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; CHECK-NEXT: movl $41, %eax
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; CHECK-NEXT: subl %edi, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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@ -195,10 +193,9 @@ define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
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define i32 @select_C_Cplus1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_C_Cplus1_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: movzbl %dil, %ecx
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: movl $42, %eax
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: subl %edi, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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@ -165,9 +165,8 @@ define i32 @select_0_or_1s_signext(i1 signext %cond) {
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;
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; X64-LABEL: select_0_or_1s_signext:
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; X64: # BB#0:
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; X64-NEXT: andb $1, %dil
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: decl %eax
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; X64-NEXT: notl %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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%not = xor i1 %cond, 1
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%sext = sext i1 %not to i32
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@ -197,13 +197,11 @@ define void @int12_int12_pair(i12 signext %tmp1, i12 signext %tmp2, i24* %ref.tm
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define void @int7_int7_pair(i7 signext %tmp1, i7 signext %tmp2, i14* %ref.tmp) {
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; CHECK-LABEL: int7_int7_pair:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: shll $7, %eax
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; CHECK-NEXT: andb $127, %dil
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; CHECK-NEXT: movzbl %dil, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: andl $16383, %ecx # imm = 0x3FFF
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; CHECK-NEXT: movw %cx, (%rdx)
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; CHECK-NEXT: shll $7, %esi
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; CHECK-NEXT: andl $127, %edi
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; CHECK-NEXT: orl %esi, %edi
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; CHECK-NEXT: andl $16383, %edi # imm = 0x3FFF
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; CHECK-NEXT: movw %di, (%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i7 %tmp2 to i14
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%t2 = shl nuw i14 %t1, 7
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