forked from OSchip/llvm-project
[AArch64][v8.5A] Add Memory Tagging system registers
This adds new system registers introduced by the Memory Tagging extension. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52488 llvm-svn: 343571
This commit is contained in:
Oliver Stannard
parent
4493f421ac
commit
2a5fcba94b
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@ -325,6 +325,9 @@ def : PState<"DIT", 0b11010>;
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// v8.5a Spectre Mitigation
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let Requires = [{ {AArch64::FeatureSpecRestrict} }] in
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def : PState<"SSBS", 0b11001>;
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// v8.5a Memory Tagging Extension
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let Requires = [{ {AArch64::FeatureMTE} }] in
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def : PState<"TCO", 0b11100>;
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//===----------------------------------------------------------------------===//
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// PSB instruction options.
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@ -1411,6 +1414,19 @@ def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>;
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let Requires = [{ {AArch64::FeatureSpecRestrict} }] in
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def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
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// v8.5a Memory Tagging Extension
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::FeatureMTE} }] in {
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def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>;
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def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>;
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def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>;
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def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0110, 0b0101, 0b000>;
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def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0110, 0b0101, 0b000>;
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def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0110, 0b0110, 0b000>;
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def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0110, 0b0110, 0b000>;
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def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0110, 0b0110, 0b001>;
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} // HasMTE
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// Cyclone specific system registers
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::ProcCyclone} }] in
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@ -0,0 +1,133 @@
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// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s 2>&1| FileCheck %s
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mrs tco
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mrs gcr_el1
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mrs rgsr_el1
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mrs tfsr_el1
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mrs tfsr_el2
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mrs tfsr_el3
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mrs tfsr_el12
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mrs tfsre0_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tco
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsre0_el1
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mrs tco, #0
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mrs tco, x0
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mrs gcr_el1, x1
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mrs rgsr_el1, x2
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mrs tfsr_el1, x3
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mrs tfsr_el2, x4
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mrs tfsr_el3, x5
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mrs tfsr_el12, x6
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mrs tfsre0_el1, x7
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tco, #0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tco, x0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsre0_el1
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msr tco
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msr gcr_el1
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msr rgsr_el1
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msr tfsr_el1
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msr tfsr_el2
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msr tfsr_el3
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msr tfsr_el12
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msr tfsre0_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tco
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// CHECK: too few operands for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsre0_el1
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msr x0, tco
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msr x1, gcr_el1
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msr x2, rgsr_el1
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msr x3, tfsr_el1
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msr x4, tfsr_el2
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msr x5, tfsr_el3
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msr x6, tfsr_el12
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msr x7, tfsre0_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tco
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: gcr_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: rgsr_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el2
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el3
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el12
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsre0_el1
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// Among the system registers added by MTE, only TCO can be used with MSR (imm).
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// The rest can only be used with MSR (reg).
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msr gcr_el1, #1
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msr rgsr_el1, #2
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msr tfsr_el1, #3
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msr tfsr_el2, #4
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msr tfsr_el3, #5
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msr tfsr_el12, #6
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msr tfsre0_el1, #7
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsre0_el1
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@ -58,3 +58,80 @@ dc gzva, x17
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// NOMTE: DC CGDVADP requires mte
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// NOMTE: DC CIGDVAC requires mte
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// NOMTE: DC GZVA requires mte
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mrs x0, tco
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mrs x1, gcr_el1
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mrs x2, rgsr_el1
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mrs x3, tfsr_el1
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mrs x4, tfsr_el2
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mrs x5, tfsr_el3
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mrs x6, tfsr_el12
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mrs x7, tfsre0_el1
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// CHECK: mrs x0, TCO // encoding: [0xe0,0x42,0x3b,0xd5]
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// CHECK: mrs x1, GCR_EL1 // encoding: [0xc1,0x10,0x38,0xd5]
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// CHECK: mrs x2, RGSR_EL1 // encoding: [0xa2,0x10,0x38,0xd5]
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// CHECK: mrs x3, TFSR_EL1 // encoding: [0x03,0x65,0x38,0xd5]
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// CHECK: mrs x4, TFSR_EL2 // encoding: [0x04,0x65,0x3c,0xd5]
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// CHECK: mrs x5, TFSR_EL3 // encoding: [0x05,0x66,0x3e,0xd5]
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// CHECK: mrs x6, TFSR_EL12 // encoding: [0x06,0x66,0x3d,0xd5]
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// CHECK: mrs x7, TFSRE0_EL1 // encoding: [0x27,0x66,0x38,0xd5]
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// NOMTE: expected readable system register
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// NOMTE-NEXT: tco
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// NOMTE: expected readable system register
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// NOMTE-NEXT: gcr_el1
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// NOMTE: expected readable system register
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// NOMTE-NEXT: rgsr_el1
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// NOMTE: expected readable system register
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// NOMTE-NEXT: tfsr_el1
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// NOMTE: expected readable system register
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// NOMTE-NEXT: tfsr_el2
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// NOMTE: expected readable system register
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// NOMTE-NEXT: tfsr_el3
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// NOMTE: expected readable system register
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// NOMTE-NEXT: tfsr_el12
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// NOMTE: expected readable system register
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// NOMTE-NEXT: tfsre0_el1
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msr tco, #0
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// CHECK: msr TCO, #0 // encoding: [0x9f,0x40,0x03,0xd5]
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: tco
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msr tco, x0
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msr gcr_el1, x1
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msr rgsr_el1, x2
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msr tfsr_el1, x3
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msr tfsr_el2, x4
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msr tfsr_el3, x5
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msr tfsr_el12, x6
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msr tfsre0_el1, x7
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// CHECK: msr TCO, x0 // encoding: [0xe0,0x42,0x1b,0xd5]
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// CHECK: msr GCR_EL1, x1 // encoding: [0xc1,0x10,0x18,0xd5]
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// CHECK: msr RGSR_EL1, x2 // encoding: [0xa2,0x10,0x18,0xd5]
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// CHECK: msr TFSR_EL1, x3 // encoding: [0x03,0x65,0x18,0xd5]
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// CHECK: msr TFSR_EL2, x4 // encoding: [0x04,0x65,0x1c,0xd5]
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// CHECK: msr TFSR_EL3, x5 // encoding: [0x05,0x66,0x1e,0xd5]
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// CHECK: msr TFSR_EL12, x6 // encoding: [0x06,0x66,0x1d,0xd5]
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// CHECK: msr TFSRE0_EL1, x7 // encoding: [0x27,0x66,0x18,0xd5]
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: tco
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: gcr_el1
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: rgsr_el1
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: tfsr_el1
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: tfsr_el2
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: tfsr_el3
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: tfsr_el12
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// NOMTE: expected writable system register or pstate
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// NOMTE-NEXT: tfsre0_el1
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@ -1,6 +1,6 @@
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# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOMTE
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# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE
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# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE
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[0x60,0x76,0x08,0xd5]
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[0x81,0x76,0x08,0xd5]
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@ -58,3 +58,43 @@
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# NOMTE: sys #3, c7, c13, #5, x15
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# NOMTE: sys #3, c7, c14, #5, x16
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# NOMTE: sys #3, c7, c4, #4, x17
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[0xe0,0x42,0x3b,0xd5]
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[0xc1,0x10,0x38,0xd5]
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[0xa2,0x10,0x38,0xd5]
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[0x03,0x65,0x38,0xd5]
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[0x04,0x65,0x3c,0xd5]
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[0x05,0x66,0x3e,0xd5]
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[0x06,0x66,0x3d,0xd5]
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[0x27,0x66,0x38,0xd5]
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# CHECK: mrs x0, TCO
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# CHECK: mrs x1, GCR_EL1
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# CHECK: mrs x2, RGSR_EL1
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# CHECK: mrs x3, TFSR_EL1
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# CHECK: mrs x4, TFSR_EL2
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# CHECK: mrs x5, TFSR_EL3
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# CHECK: mrs x6, TFSR_EL12
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# CHECK: mrs x7, TFSRE0_EL1
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[0x9f,0x40,0x03,0xd5]
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# CHECK: msr TCO, #0
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[0xe0,0x42,0x1b,0xd5]
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[0xc1,0x10,0x18,0xd5]
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[0xa2,0x10,0x18,0xd5]
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[0x03,0x65,0x18,0xd5]
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[0x04,0x65,0x1c,0xd5]
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[0x05,0x66,0x1e,0xd5]
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[0x06,0x66,0x1d,0xd5]
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[0x27,0x66,0x18,0xd5]
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# CHECK: msr TCO, x0
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# CHECK: msr GCR_EL1, x1
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# CHECK: msr RGSR_EL1, x2
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# CHECK: msr TFSR_EL1, x3
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# CHECK: msr TFSR_EL2, x4
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# CHECK: msr TFSR_EL3, x5
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# CHECK: msr TFSR_EL12, x6
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# CHECK: msr TFSRE0_EL1, x7
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