From 2a07221cf3029f2b55503e1c3847699eb6090ad6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 30 Mar 2020 22:01:37 -0700 Subject: [PATCH] [SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same. Differential Revision: https://reviews.llvm.org/D77092 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index c20e40e0c978..3bfc8545e544 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -4550,6 +4550,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, unsigned OpOpcode = Operand.getNode()->getOpcode(); switch (Opcode) { + case ISD::FREEZE: + assert(VT == Operand.getValueType() && "Unexpected VT!"); + break; case ISD::TokenFactor: case ISD::MERGE_VALUES: case ISD::CONCAT_VECTORS: