[SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.

Differential Revision: https://reviews.llvm.org/D77092

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -4550,6 +4550,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
 
   unsigned OpOpcode = Operand.getNode()->getOpcode();
   switch (Opcode) {
+  case ISD::FREEZE:
+    assert(VT == Operand.getValueType() && "Unexpected VT!");
+    break;
   case ISD::TokenFactor:
   case ISD::MERGE_VALUES:
   case ISD::CONCAT_VECTORS: