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Allow certain lea instructions to be rematerialized. 

llvm-svn: 48855
This commit is contained in:
Evan Cheng 2008-03-27 01:41:09 +00:00
parent 4fb07c6500
commit 29e62a59f3
3 changed files with 68 additions and 35 deletions
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1
llvm/lib/Target/X86/X86Instr64bit.td
View File

@ -154,6 +154,7 @@ def LEA64_32r : I<0x8D, MRMSrcMem,
"lea{l}\t{$src|$dst}, {$dst|$src}", "lea{l}\t{$src|$dst}, {$dst|$src}",
[(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>; [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
let isReMaterializable = 1 in
def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
"lea{q}\t{$src|$dst}, {$dst|$src}", "lea{q}\t{$src|$dst}, {$dst|$src}",
[(set GR64:$dst, lea64addr:$src)]>; [(set GR64:$dst, lea64addr:$src)]>;

101
llvm/lib/Target/X86/X86InstrInfo.cpp
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@ -734,46 +734,77 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
} }
static bool regIsPICBase(MachineInstr *MI, unsigned BaseReg) {
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
bool isPICBase = false;
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
E = MRI.def_end(); I != E; ++I) {
MachineInstr *DefMI = I.getOperand().getParent();
if (DefMI->getOpcode() != X86::MOVPC32r)
return false;
assert(!isPICBase && "More than one PIC base?");
isPICBase = true;
}
return isPICBase;
}
bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const { bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: break; default: break;
case X86::MOV8rm: case X86::MOV8rm:
case X86::MOV16rm: case X86::MOV16rm:
case X86::MOV16_rm: case X86::MOV16_rm:
case X86::MOV32rm: case X86::MOV32rm:
case X86::MOV32_rm: case X86::MOV32_rm:
case X86::MOV64rm: case X86::MOV64rm:
case X86::LD_Fp64m: case X86::LD_Fp64m:
case X86::MOVSSrm: case X86::MOVSSrm:
case X86::MOVSDrm: case X86::MOVSDrm:
case X86::MOVAPSrm: case X86::MOVAPSrm:
case X86::MOVAPDrm: case X86::MOVAPDrm:
case X86::MMX_MOVD64rm: case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm: case X86::MMX_MOVQ64rm: {
// Loads from constant pools are trivially rematerializable. // Loads from constant pools are trivially rematerializable.
if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() && if (MI->getOperand(1).isReg() &&
MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 1 && MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
MI->getOperand(3).getReg() == 0) { MI->getOperand(4).isCPI()) {
unsigned BaseReg = MI->getOperand(1).getReg(); unsigned BaseReg = MI->getOperand(1).getReg();
if (BaseReg == 0) if (BaseReg == 0)
return true; return true;
// Allow re-materialization of PIC load. // Allow re-materialization of PIC load.
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
bool isPICBase = false; bool isPICBase = false;
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
E = MRI.def_end(); I != E; ++I) { E = MRI.def_end(); I != E; ++I) {
MachineInstr *DefMI = I.getOperand().getParent(); MachineInstr *DefMI = I.getOperand().getParent();
if (DefMI->getOpcode() != X86::MOVPC32r) if (DefMI->getOpcode() != X86::MOVPC32r)
return false; return false;
assert(!isPICBase && "More than one PIC base?"); assert(!isPICBase && "More than one PIC base?");
isPICBase = true; isPICBase = true;
} }
return isPICBase; return isPICBase;
}
return false;
} }
return false; case X86::LEA32r:
case X86::LEA64r: {
if (MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
!MI->getOperand(4).isReg()) {
// lea fi#, lea GV, etc. are all rematerializable.
unsigned BaseReg = MI->getOperand(1).getReg();
if (BaseReg == 0)
return true;
// Allow re-materialization of lea PICBase + x.
return regIsPICBase(MI, BaseReg);
}
return false;
}
} }
// All other instructions marked M_REMATERIALIZABLE are always trivially // All other instructions marked M_REMATERIALIZABLE are always trivially
// rematerializable. // rematerializable.
return true; return true;

1
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -464,6 +464,7 @@ let neverHasSideEffects = 1 in
def LEA16r : I<0x8D, MRMSrcMem, def LEA16r : I<0x8D, MRMSrcMem,
(outs GR16:$dst), (ins i32mem:$src), (outs GR16:$dst), (ins i32mem:$src),
"lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
let isReMaterializable = 1 in
def LEA32r : I<0x8D, MRMSrcMem, def LEA32r : I<0x8D, MRMSrcMem,
(outs GR32:$dst), (ins lea32mem:$src), (outs GR32:$dst), (ins lea32mem:$src),
"lea{l}\t{$src|$dst}, {$dst|$src}", "lea{l}\t{$src|$dst}, {$dst|$src}",