forked from OSchip/llvm-project
Initial Assembly profiler for mips64
Summary: This is initial implementation of assembly profiler which only scans prologue/epilogue assembly instructions to create CFI instructions. Reviewers: clayborg, jasonmolenda Differential Revision: http://reviews.llvm.org/D7696 llvm-svn: 232619
This commit is contained in:
Bhushan D. Attarde
parent
41c56755be
commit
29e5937cd9
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@ -49,6 +49,7 @@ set( LLDB_USED_LIBS
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lldbPluginABISysV_ppc64
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lldbPluginInstructionARM
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lldbPluginInstructionARM64
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lldbPluginInstructionMIPS64
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lldbPluginObjectFilePECOFF
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lldbPluginOSPython
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lldbPluginMemoryHistoryASan
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@ -45,6 +45,7 @@ USEDLIBS = lldbAPI.a \
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lldbPluginDynamicLoaderMacOSX.a \
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lldbPluginEmulateInstructionARM.a \
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lldbPluginEmulateInstructionARM64.a \
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lldbPluginEmulateInstructionMIPS64.a \
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lldbPluginInstrumentationRuntimeAddressSanitizer.a \
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lldbPluginLanguageRuntimeCPlusPlusItaniumABI.a \
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lldbPluginLanguageRuntimeObjCAppleObjCRuntime.a \
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@ -1,2 +1,3 @@
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add_subdirectory(ARM)
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add_subdirectory(ARM64)
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add_subdirectory(MIPS64)
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@ -0,0 +1,5 @@
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set(LLVM_NO_RTTI 1)
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add_lldb_library(lldbPluginInstructionMIPS64
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EmulateInstructionMIPS64.cpp
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)
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@ -0,0 +1,444 @@
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//===-- EmulateInstructionMIPS64.cpp -------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "EmulateInstructionMIPS64.h"
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#include <stdlib.h>
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#include "lldb/Core/ArchSpec.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/ConstString.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Core/Stream.h"
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#include "lldb/Symbol/UnwindPlan.h"
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#include "llvm/ADT/STLExtras.h"
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//#include "llvm/Support/MathExtras.h" // for SignExtend32 template function
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#include "Plugins/Process/Utility/InstructionUtils.h"
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#include "Plugins/Process/Utility/RegisterContext_mips64.h"
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using namespace lldb;
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using namespace lldb_private;
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#define UInt(x) ((uint64_t)x)
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#define integer int64_t
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//----------------------------------------------------------------------
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//
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// EmulateInstructionMIPS64 implementation
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//
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//----------------------------------------------------------------------
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void
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EmulateInstructionMIPS64::Initialize ()
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{
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PluginManager::RegisterPlugin (GetPluginNameStatic (),
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GetPluginDescriptionStatic (),
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CreateInstance);
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}
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void
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EmulateInstructionMIPS64::Terminate ()
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{
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PluginManager::UnregisterPlugin (CreateInstance);
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}
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ConstString
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EmulateInstructionMIPS64::GetPluginNameStatic ()
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{
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ConstString g_plugin_name ("lldb.emulate-instruction.mips64");
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return g_plugin_name;
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}
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lldb_private::ConstString
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EmulateInstructionMIPS64::GetPluginName()
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{
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static ConstString g_plugin_name ("EmulateInstructionMIPS64");
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return g_plugin_name;
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}
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const char *
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EmulateInstructionMIPS64::GetPluginDescriptionStatic ()
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{
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return "Emulate instructions for the MIPS64 architecture.";
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}
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EmulateInstruction *
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EmulateInstructionMIPS64::CreateInstance (const ArchSpec &arch, InstructionType inst_type)
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{
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if (EmulateInstructionMIPS64::SupportsEmulatingInstructionsOfTypeStatic(inst_type))
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{
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if (arch.GetTriple().getArch() == llvm::Triple::mips64)
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{
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std::auto_ptr<EmulateInstructionMIPS64> emulate_insn_ap (new EmulateInstructionMIPS64 (arch));
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if (emulate_insn_ap.get())
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return emulate_insn_ap.release();
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}
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}
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return NULL;
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}
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bool
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EmulateInstructionMIPS64::SetTargetTriple (const ArchSpec &arch)
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{
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if (arch.GetTriple().getArch () == llvm::Triple::mips64)
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return true;
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return false;
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}
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const char *
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EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name)
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{
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if (alternate_name)
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{
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switch (reg_num)
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{
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case gcc_dwarf_sp_mips64: return "r29";
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case gcc_dwarf_r30_mips64: return "r30";
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case gcc_dwarf_ra_mips64: return "r31";
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default:
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break;
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}
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return nullptr;
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}
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switch (reg_num)
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{
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case gcc_dwarf_zero_mips64: return "r0";
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case gcc_dwarf_r1_mips64: return "r1";
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case gcc_dwarf_r2_mips64: return "r2";
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case gcc_dwarf_r3_mips64: return "r3";
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case gcc_dwarf_r4_mips64: return "r4";
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case gcc_dwarf_r5_mips64: return "r5";
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case gcc_dwarf_r6_mips64: return "r6";
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case gcc_dwarf_r7_mips64: return "r7";
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case gcc_dwarf_r8_mips64: return "r8";
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case gcc_dwarf_r9_mips64: return "r9";
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case gcc_dwarf_r10_mips64: return "r10";
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case gcc_dwarf_r11_mips64: return "r11";
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case gcc_dwarf_r12_mips64: return "r12";
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case gcc_dwarf_r13_mips64: return "r13";
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case gcc_dwarf_r14_mips64: return "r14";
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case gcc_dwarf_r15_mips64: return "r15";
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case gcc_dwarf_r16_mips64: return "r16";
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case gcc_dwarf_r17_mips64: return "r17";
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case gcc_dwarf_r18_mips64: return "r18";
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case gcc_dwarf_r19_mips64: return "r19";
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case gcc_dwarf_r20_mips64: return "r20";
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case gcc_dwarf_r21_mips64: return "r21";
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case gcc_dwarf_r22_mips64: return "r22";
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case gcc_dwarf_r23_mips64: return "r23";
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case gcc_dwarf_r24_mips64: return "r24";
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case gcc_dwarf_r25_mips64: return "r25";
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case gcc_dwarf_r26_mips64: return "r26";
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case gcc_dwarf_r27_mips64: return "r27";
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case gcc_dwarf_gp_mips64: return "gp";
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case gcc_dwarf_sp_mips64: return "sp";
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case gcc_dwarf_r30_mips64: return "fp";
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case gcc_dwarf_ra_mips64: return "ra";
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case gcc_dwarf_sr_mips64: return "sr";
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case gcc_dwarf_lo_mips64: return "lo";
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case gcc_dwarf_hi_mips64: return "hi";
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case gcc_dwarf_bad_mips64: return "bad";
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case gcc_dwarf_cause_mips64: return "cause";
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case gcc_dwarf_pc_mips64: return "pc";
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}
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return nullptr;
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}
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bool
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EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num, RegisterInfo ®_info)
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{
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if (reg_kind == eRegisterKindGeneric)
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{
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switch (reg_num)
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{
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case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_pc_mips64; break;
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case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sp_mips64; break;
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case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_r30_mips64; break;
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case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_ra_mips64; break;
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case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sr_mips64; break;
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return true;
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default: return false;
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}
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}
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if (reg_kind == eRegisterKindDWARF)
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{
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::memset (®_info, 0, sizeof(RegisterInfo));
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::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
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if (reg_num == gcc_dwarf_sr_mips64)
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{
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reg_info.byte_size = 4;
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reg_info.format = eFormatHex;
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reg_info.encoding = eEncodingUint;
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}
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else if (reg_num >= gcc_dwarf_zero_mips64 && reg_num <= gcc_dwarf_pc_mips64)
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{
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reg_info.byte_size = 8;
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reg_info.format = eFormatHex;
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reg_info.encoding = eEncodingUint;
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}
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else
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{
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return false;
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}
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reg_info.name = GetRegisterName (reg_num, false);
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reg_info.alt_name = GetRegisterName (reg_num, true);
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reg_info.kinds[eRegisterKindDWARF] = reg_num;
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switch (reg_num)
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{
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case gcc_dwarf_r30_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break;
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case gcc_dwarf_ra_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break;
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case gcc_dwarf_sp_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break;
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case gcc_dwarf_pc_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break;
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case gcc_dwarf_sr_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break;
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default: break;
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}
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return true;
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}
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return false;
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}
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EmulateInstructionMIPS64::Opcode*
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EmulateInstructionMIPS64::GetOpcodeForInstruction (const uint32_t opcode)
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{
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static EmulateInstructionMIPS64::Opcode
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g_opcodes[] =
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{
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//----------------------------------------------------------------------
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// Prologue/Epilogue instructions
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//----------------------------------------------------------------------
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// stack adjustment
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{ 0xffff0000, 0x67bd0000, &EmulateInstructionMIPS64::Emulate_addsp_imm, "DADDIU rt, rs, immediate" },
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// store register
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{ 0xfc000000, 0xfc000000, &EmulateInstructionMIPS64::Emulate_store, "SD rt, offset(Rn)" },
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// Load register
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{ 0xfc000000, 0xdc000000, &EmulateInstructionMIPS64::Emulate_load, "LD rt, offset(base)" },
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};
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static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);
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for (size_t i=0; i<k_num_mips_opcodes; ++i)
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{
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if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value)
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return &g_opcodes[i];
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}
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return NULL;
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}
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bool
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EmulateInstructionMIPS64::ReadInstruction ()
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{
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bool success = false;
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m_addr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success);
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if (success)
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{
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Context read_inst_context;
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read_inst_context.type = eContextReadOpcode;
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read_inst_context.SetNoArgs ();
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m_opcode.SetOpcode32 (ReadMemoryUnsigned (read_inst_context, m_addr, 4, 0, &success), GetByteOrder());
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}
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if (!success)
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m_addr = LLDB_INVALID_ADDRESS;
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return success;
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}
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bool
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EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options)
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{
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uint32_t opcode = m_opcode.GetOpcode32();
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if (GetByteOrder() == eByteOrderBig)
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opcode = llvm::ByteSwap_32(opcode);
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Opcode *opcode_data = GetOpcodeForInstruction(opcode);
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bool success = false;
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if (opcode_data == NULL)
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return false;
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// Call the Emulate... function.
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success = (this->*opcode_data->callback) (opcode);
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if (!success)
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return false;
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return true;
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}
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bool
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EmulateInstructionMIPS64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan)
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{
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unwind_plan.Clear();
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unwind_plan.SetRegisterKind (eRegisterKindDWARF);
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UnwindPlan::RowSP row(new UnwindPlan::Row);
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const bool can_replace = false;
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// Our previous Call Frame Address is the stack pointer
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row->GetCFAValue().SetIsRegisterPlusOffset(gcc_dwarf_sp_mips64, 0);
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// Our previous PC is in the RA
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row->SetRegisterLocationToRegister(gcc_dwarf_pc_mips64, gcc_dwarf_ra_mips64, can_replace);
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unwind_plan.AppendRow (row);
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// All other registers are the same.
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unwind_plan.SetSourceName ("EmulateInstructionMIPS64");
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unwind_plan.SetSourcedFromCompiler (eLazyBoolNo);
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unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes);
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return true;
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}
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bool
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EmulateInstructionMIPS64::nonvolatile_reg_p (uint64_t regnum)
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{
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switch (regnum)
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{
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case gcc_dwarf_r16_mips64:
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case gcc_dwarf_r17_mips64:
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case gcc_dwarf_r18_mips64:
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case gcc_dwarf_r19_mips64:
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case gcc_dwarf_r20_mips64:
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case gcc_dwarf_r21_mips64:
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case gcc_dwarf_r22_mips64:
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case gcc_dwarf_r23_mips64:
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case gcc_dwarf_sp_mips64:
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case gcc_dwarf_r30_mips64:
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case gcc_dwarf_ra_mips64:
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return true;
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default:
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return false;
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}
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return false;
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}
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bool
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EmulateInstructionMIPS64::Emulate_addsp_imm (const uint32_t opcode)
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{
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/* Get immediate operand */
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const uint32_t imm16 = Bits32(opcode, 15, 0);
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bool success = false;
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uint64_t result;
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uint64_t imm = SignedBits(imm16, 15, 0);
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uint64_t operand1 = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_sp_mips64, 0, &success);
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uint64_t operand2 = imm;
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result = operand1 + operand2;
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Context context;
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RegisterInfo reg_info_Rn;
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if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips64, reg_info_Rn))
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context.SetRegisterPlusOffset (reg_info_Rn, imm);
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/* We are allocating bytes on stack */
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context.type = eContextAdjustStackPointer;
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WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips64, result);
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_store (const uint32_t opcode)
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{
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uint32_t imm16 = Bits32(opcode, 15, 0);
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uint32_t Rt = Bits32(opcode, 20, 16);
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uint32_t base = Bits32(opcode, 25, 21);
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uint64_t imm = SignedBits(imm16, 15, 0);
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uint64_t address;
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integer n = UInt(base);
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integer t = UInt(Rt);
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RegisterValue data_Rt;
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RegisterInfo reg_info_base;
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RegisterInfo reg_info_Rt;
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if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + n, reg_info_base))
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return false;
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if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + t, reg_info_Rt))
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return false;
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bool success = false;
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Context context_t;
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/* We look for sp based non-volatile register stores */
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if (n == 29 && nonvolatile_reg_p(t))
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address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_sp_mips64, 0, &success);
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else
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return false;
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/* Calculate address to store */
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address = address + imm;
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context_t.type = eContextPushRegisterOnStack;
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context_t.SetRegisterToRegisterPlusOffset (reg_info_Rt, reg_info_base, 0);
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uint8_t buffer [RegisterValue::kMaxRegisterByteSize];
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Error error;
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if (!ReadRegister (®_info_Rt, data_Rt))
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return false;
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if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, eByteOrderLittle, error) == 0)
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return false;
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if (!WriteMemory(context_t, address, buffer, reg_info_Rt.byte_size))
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return false;
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_load (const uint32_t opcode)
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{
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||||
uint32_t Rt = Bits32(opcode, 20, 16);
|
||||
uint32_t base = Bits32(opcode, 25, 21);
|
||||
|
||||
integer n = UInt(base);
|
||||
integer t = UInt(Rt);
|
||||
|
||||
RegisterValue data_Rt;
|
||||
RegisterInfo reg_info_Rt;
|
||||
|
||||
if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + t, reg_info_Rt))
|
||||
return false;
|
||||
|
||||
Context context_t;
|
||||
|
||||
/* We are looking for "saved register" being restored from stack */
|
||||
if (!n == 29 || !nonvolatile_reg_p(t))
|
||||
return false;
|
||||
|
||||
context_t.type = eContextRegisterLoad;
|
||||
|
||||
if (!WriteRegister (context_t, ®_info_Rt, data_Rt))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
//===-- EmulateInstructionMIPS64.h ------------------------------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef EmulateInstructionMIPS64_h_
|
||||
#define EmulateInstructionMIPS64_h_
|
||||
|
||||
#include "lldb/Core/EmulateInstruction.h"
|
||||
#include "lldb/Core/Error.h"
|
||||
#include "lldb/Interpreter/OptionValue.h"
|
||||
|
||||
class EmulateInstructionMIPS64 : public lldb_private::EmulateInstruction
|
||||
{
|
||||
public:
|
||||
static void
|
||||
Initialize ();
|
||||
|
||||
static void
|
||||
Terminate ();
|
||||
|
||||
static lldb_private::ConstString
|
||||
GetPluginNameStatic ();
|
||||
|
||||
static const char *
|
||||
GetPluginDescriptionStatic ();
|
||||
|
||||
static lldb_private::EmulateInstruction *
|
||||
CreateInstance (const lldb_private::ArchSpec &arch,
|
||||
lldb_private::InstructionType inst_type);
|
||||
|
||||
static bool
|
||||
SupportsEmulatingInstructionsOfTypeStatic (lldb_private::InstructionType inst_type)
|
||||
{
|
||||
switch (inst_type)
|
||||
{
|
||||
case lldb_private::eInstructionTypeAny:
|
||||
case lldb_private::eInstructionTypePrologueEpilogue:
|
||||
return true;
|
||||
|
||||
case lldb_private::eInstructionTypePCModifying:
|
||||
case lldb_private::eInstructionTypeAll:
|
||||
return false;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
virtual lldb_private::ConstString
|
||||
GetPluginName();
|
||||
|
||||
virtual lldb_private::ConstString
|
||||
GetShortPluginName()
|
||||
{
|
||||
return GetPluginNameStatic();
|
||||
}
|
||||
|
||||
virtual uint32_t
|
||||
GetPluginVersion()
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool
|
||||
SetTargetTriple (const lldb_private::ArchSpec &arch);
|
||||
|
||||
EmulateInstructionMIPS64 (const lldb_private::ArchSpec &arch) :
|
||||
EmulateInstruction (arch)
|
||||
{
|
||||
}
|
||||
|
||||
virtual bool
|
||||
SupportsEmulatingInstructionsOfType (lldb_private::InstructionType inst_type)
|
||||
{
|
||||
return SupportsEmulatingInstructionsOfTypeStatic (inst_type);
|
||||
}
|
||||
|
||||
virtual bool
|
||||
ReadInstruction ();
|
||||
|
||||
virtual bool
|
||||
EvaluateInstruction (uint32_t evaluate_options);
|
||||
|
||||
virtual bool
|
||||
TestEmulation (lldb_private::Stream *out_stream,
|
||||
lldb_private::ArchSpec &arch,
|
||||
lldb_private::OptionValueDictionary *test_data)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
virtual bool
|
||||
GetRegisterInfo (lldb::RegisterKind reg_kind,
|
||||
uint32_t reg_num,
|
||||
lldb_private::RegisterInfo ®_info);
|
||||
|
||||
virtual bool
|
||||
CreateFunctionEntryUnwind (lldb_private::UnwindPlan &unwind_plan);
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t mask;
|
||||
uint32_t value;
|
||||
bool (EmulateInstructionMIPS64::*callback) (const uint32_t opcode);
|
||||
const char *name;
|
||||
} Opcode;
|
||||
|
||||
static Opcode*
|
||||
GetOpcodeForInstruction (const uint32_t opcode);
|
||||
|
||||
bool
|
||||
Emulate_addsp_imm (const uint32_t opcode);
|
||||
|
||||
bool
|
||||
Emulate_store (const uint32_t opcode);
|
||||
|
||||
bool
|
||||
Emulate_load (const uint32_t opcode);
|
||||
|
||||
bool
|
||||
nonvolatile_reg_p (uint64_t regnum);
|
||||
|
||||
const char *
|
||||
GetRegisterName (unsigned reg_num, bool altnernate_name);
|
||||
|
||||
};
|
||||
|
||||
#endif // EmulateInstructionMIPS64_h_
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
##===- source/Plugins/Instruction/MIPS64/Makefile -------------*- Makefile -*-===##
|
||||
#
|
||||
# The LLVM Compiler Infrastructure
|
||||
#
|
||||
# This file is distributed under the University of Illinois Open Source
|
||||
# License. See LICENSE.TXT for details.
|
||||
#
|
||||
##===----------------------------------------------------------------------===##
|
||||
|
||||
LLDB_LEVEL := ../../../..
|
||||
LIBRARYNAME := lldbPluginEmulateInstructionMIPS64
|
||||
BUILD_ARCHIVE = 1
|
||||
|
||||
include $(LLDB_LEVEL)/Makefile
|
||||
|
|
@ -19,7 +19,7 @@ PARALLEL_DIRS := ABI/MacOSX-arm ABI/MacOSX-arm64 ABI/MacOSX-i386 ABI/SysV-x86_64
|
|||
ObjectContainer/Universal-Mach-O ObjectFile/Mach-O \
|
||||
ObjectFile/JIT SymbolFile/DWARF SymbolFile/Symtab Process/Utility \
|
||||
DynamicLoader/Static Platform Process/gdb-remote \
|
||||
Instruction/ARM Instruction/ARM64 \
|
||||
Instruction/ARM Instruction/ARM64 Instruction/MIPS64 \
|
||||
UnwindAssembly/InstEmulation UnwindAssembly/x86 \
|
||||
LanguageRuntime/CPlusPlus/ItaniumABI \
|
||||
LanguageRuntime/ObjC/AppleObjCRuntime \
|
||||
|
|
|
|||
|
|
@ -610,7 +610,6 @@ UnwindAssemblyInstEmulation::WriteRegister (EmulateInstruction *instruction,
|
|||
case EmulateInstruction::eContextRegisterPlusOffset:
|
||||
case EmulateInstruction::eContextAdjustPC:
|
||||
case EmulateInstruction::eContextRegisterStore:
|
||||
case EmulateInstruction::eContextRegisterLoad:
|
||||
case EmulateInstruction::eContextAbsoluteBranchRegister:
|
||||
case EmulateInstruction::eContextSupervisorCall:
|
||||
case EmulateInstruction::eContextTableBranchReadMemory:
|
||||
|
|
@ -634,6 +633,35 @@ UnwindAssemblyInstEmulation::WriteRegister (EmulateInstruction *instruction,
|
|||
// }
|
||||
break;
|
||||
|
||||
case EmulateInstruction::eContextRegisterLoad:
|
||||
{
|
||||
const uint32_t unwind_reg_kind = m_unwind_plan_ptr->GetRegisterKind();
|
||||
const uint32_t reg_num = reg_info->kinds[unwind_reg_kind];
|
||||
if (reg_num != LLDB_INVALID_REGNUM)
|
||||
{
|
||||
m_curr_row->SetRegisterLocationToRegister (reg_num, reg_num, must_replace);
|
||||
m_curr_row_modified = true;
|
||||
m_curr_insn_restored_a_register = true;
|
||||
|
||||
if (reg_info->kinds[eRegisterKindGeneric] == LLDB_REGNUM_GENERIC_RA)
|
||||
{
|
||||
// This load was restoring the return address register,
|
||||
// so this is also how we will unwind the PC...
|
||||
RegisterInfo pc_reg_info;
|
||||
if (instruction->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, pc_reg_info))
|
||||
{
|
||||
uint32_t pc_reg_num = pc_reg_info.kinds[unwind_reg_kind];
|
||||
if (pc_reg_num != LLDB_INVALID_REGNUM)
|
||||
{
|
||||
m_curr_row->SetRegisterLocationToRegister (pc_reg_num, reg_num, must_replace);
|
||||
m_curr_row_modified = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case EmulateInstruction::eContextRelativeBranchImmediate:
|
||||
{
|
||||
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#include "Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.h"
|
||||
#include "Plugins/Instruction/ARM/EmulateInstructionARM.h"
|
||||
#include "Plugins/Instruction/ARM64/EmulateInstructionARM64.h"
|
||||
#include "Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h"
|
||||
#include "Plugins/JITLoader/GDB/JITLoaderGDB.h"
|
||||
#include "Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.h"
|
||||
#include "Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.h"
|
||||
|
|
@ -224,6 +225,7 @@ lldb_private::Initialize ()
|
|||
UnwindAssembly_x86::Initialize();
|
||||
EmulateInstructionARM::Initialize();
|
||||
EmulateInstructionARM64::Initialize();
|
||||
EmulateInstructionMIPS64::Initialize();
|
||||
SymbolFileDWARFDebugMap::Initialize();
|
||||
ItaniumABILanguageRuntime::Initialize();
|
||||
AppleObjCRuntimeV2::Initialize();
|
||||
|
|
@ -339,6 +341,7 @@ lldb_private::Terminate ()
|
|||
UnwindAssemblyInstEmulation::Terminate();
|
||||
EmulateInstructionARM::Terminate();
|
||||
EmulateInstructionARM64::Terminate();
|
||||
EmulateInstructionMIPS64::Terminate();
|
||||
SymbolFileDWARFDebugMap::Terminate();
|
||||
ItaniumABILanguageRuntime::Terminate();
|
||||
AppleObjCRuntimeV2::Terminate();
|
||||
|
|
|
|||
Loading…
Reference in New Issue