forked from OSchip/llvm-project
[AArch64] Simplify prolog/epilog callee save/restore. NFC.
Summary: Factor out common code for callee-save register pair calculation. This is intended to simplify follow-on changes that reduce the number of registers saved/restored. Depends on D16732 Reviewers: mcrosier, jmolloy, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16734 llvm-svn: 259384
This commit is contained in:
Geoff Berry
parent
f27e752fe8
commit
29d4a695f4
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@ -668,20 +668,29 @@ static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
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return getKillRegState(LRKill);
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}
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bool AArch64FrameLowering::spillCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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struct RegPairInfo {
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RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {}
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unsigned Reg1;
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unsigned Reg2;
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int FrameIdx;
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int Offset;
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bool IsGPR;
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};
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static void
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computeCalleeSaveRegisterPairs(const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI,
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SmallVectorImpl<RegPairInfo> &RegPairs) {
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unsigned Count = CSI.size();
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DebugLoc DL;
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assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
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for (unsigned i = 0; i < Count; i += 2) {
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unsigned idx = Count - i - 2;
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unsigned Reg1 = CSI[idx].getReg();
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unsigned Reg2 = CSI[idx + 1].getReg();
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RegPairInfo RPI;
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RPI.Reg1 = CSI[idx].getReg();
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RPI.Reg2 = CSI[idx + 1].getReg();
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// GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
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// list to come in sorted by frame index so that we can issue the store
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// pair instructions directly. Assert if we see anything otherwise.
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@ -690,9 +699,44 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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// getCalleeSavedRegs(), so they will always be in-order, as well.
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assert(CSI[idx].getFrameIdx() + 1 == CSI[idx + 1].getFrameIdx() &&
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"Out of order callee saved regs!");
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unsigned StrOpc;
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assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
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assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
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RPI.FrameIdx = CSI[idx + 1].getFrameIdx();
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if (AArch64::GPR64RegClass.contains(RPI.Reg1))
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RPI.IsGPR = true;
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else if (AArch64::FPR64RegClass.contains(RPI.Reg1))
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RPI.IsGPR = false;
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else
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llvm_unreachable("Unexpected callee saved register!");
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// Compute offset: i = 0 => offset = Count;
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// i = 2 => offset = -(Count - 2) + Count = 2 = i; etc.
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RPI.Offset = (i == 0) ? Count : i;
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assert((RPI.Offset >= -64 && RPI.Offset <= 63) &&
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"Offset out of bounds for LDP/STP immediate");
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RegPairs.push_back(RPI);
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}
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}
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bool AArch64FrameLowering::spillCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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DebugLoc DL;
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SmallVector<RegPairInfo, 8> RegPairs;
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computeCalleeSaveRegisterPairs(CSI, TRI, RegPairs);
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for (auto RPII = RegPairs.begin(), RPIE = RegPairs.end(); RPII != RPIE;
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++RPII) {
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RegPairInfo RPI = *RPII;
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unsigned Reg1 = RPI.Reg1;
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unsigned Reg2 = RPI.Reg2;
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unsigned StrOpc;
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// Issue sequence of non-sp increment and pi sp spills for cs regs. The
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// first spill is a pre-increment that allocates the stack.
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// For example:
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@ -701,35 +745,28 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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// stp fp, lr, [sp, #32] // addImm(+4)
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// Rationale: This sequence saves uop updates compared to a sequence of
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// pre-increment spills like stp xi,xj,[sp,#-16]!
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// Note: Similar rational and sequence for restores in epilog.
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if (AArch64::GPR64RegClass.contains(Reg1)) {
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assert(AArch64::GPR64RegClass.contains(Reg2) &&
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"Expected GPR64 callee-saved register pair!");
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// Note: Similar rationale and sequence for restores in epilog.
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bool BumpSP = RPII == RegPairs.begin();
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if (RPI.IsGPR) {
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// For first spill use pre-increment store.
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if (i == 0)
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if (BumpSP)
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StrOpc = AArch64::STPXpre;
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else
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StrOpc = AArch64::STPXi;
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} else if (AArch64::FPR64RegClass.contains(Reg1)) {
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assert(AArch64::FPR64RegClass.contains(Reg2) &&
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"Expected FPR64 callee-saved register pair!");
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} else {
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// For first spill use pre-increment store.
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if (i == 0)
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if (BumpSP)
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StrOpc = AArch64::STPDpre;
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else
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StrOpc = AArch64::STPDi;
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} else
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llvm_unreachable("Unexpected callee saved register!");
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}
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DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
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<< TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
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<< ", " << CSI[idx + 1].getFrameIdx() << ")\n");
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// Compute offset: i = 0 => offset = -Count;
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// i = 2 => offset = -(Count - 2) + Count = 2 = i; etc.
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const int Offset = (i == 0) ? -Count : i;
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assert((Offset >= -64 && Offset <= 63) &&
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"Offset out of bounds for STP immediate");
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<< TRI->getName(Reg2) << ") -> fi#(" << RPI.FrameIdx
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<< ", " << RPI.FrameIdx+1 << ")\n");
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const int Offset = BumpSP ? -RPI.Offset : RPI.Offset;
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
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if (StrOpc == AArch64::STPDpre || StrOpc == AArch64::STPXpre)
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if (BumpSP)
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MIB.addReg(AArch64::SP, RegState::Define);
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MBB.addLiveIn(Reg1);
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@ -749,21 +786,20 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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unsigned Count = CSI.size();
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DebugLoc DL;
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assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
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SmallVector<RegPairInfo, 8> RegPairs;
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if (MI != MBB.end())
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DL = MI->getDebugLoc();
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for (unsigned i = 0; i < Count; i += 2) {
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unsigned Reg1 = CSI[i].getReg();
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unsigned Reg2 = CSI[i + 1].getReg();
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// GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
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// list to come in sorted by frame index so that we can issue the store
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// pair instructions directly. Assert if we see anything otherwise.
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assert(CSI[i].getFrameIdx() + 1 == CSI[i + 1].getFrameIdx() &&
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"Out of order callee saved regs!");
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computeCalleeSaveRegisterPairs(CSI, TRI, RegPairs);
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for (auto RPII = RegPairs.rbegin(), RPIE = RegPairs.rend(); RPII != RPIE;
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++RPII) {
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RegPairInfo RPI = *RPII;
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unsigned Reg1 = RPI.Reg1;
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unsigned Reg2 = RPI.Reg2;
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// Issue sequence of non-sp increment and sp-pi restores for cs regs. Only
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// the last load is sp-pi post-increment and de-allocates the stack:
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// For example:
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@ -772,36 +808,25 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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// ldp x22, x21, [sp], #48 // addImm(+6)
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// Note: see comment in spillCalleeSavedRegisters()
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unsigned LdrOpc;
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assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
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assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
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if (AArch64::GPR64RegClass.contains(Reg1)) {
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assert(AArch64::GPR64RegClass.contains(Reg2) &&
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"Expected GPR64 callee-saved register pair!");
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if (i == Count - 2)
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bool BumpSP = RPII == std::prev(RegPairs.rend());
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if (RPI.IsGPR) {
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if (BumpSP)
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LdrOpc = AArch64::LDPXpost;
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else
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LdrOpc = AArch64::LDPXi;
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} else if (AArch64::FPR64RegClass.contains(Reg1)) {
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assert(AArch64::FPR64RegClass.contains(Reg2) &&
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"Expected FPR64 callee-saved register pair!");
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if (i == Count - 2)
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} else {
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if (BumpSP)
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LdrOpc = AArch64::LDPDpost;
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else
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LdrOpc = AArch64::LDPDi;
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} else
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llvm_unreachable("Unexpected callee saved register!");
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}
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DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
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<< TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx()
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<< ", " << CSI[i + 1].getFrameIdx() << ")\n");
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<< TRI->getName(Reg2) << ") -> fi#(" << RPI.FrameIdx
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<< ", " << RPI.FrameIdx+1 << ")\n");
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// Compute offset: i = 0 => offset = Count - 2; i = 2 => offset = Count - 4;
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// etc.
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const int Offset = (i == Count - 2) ? Count : Count - i - 2;
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assert((Offset >= -64 && Offset <= 63) &&
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"Offset out of bounds for LDP immediate");
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const int Offset = RPI.Offset;
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
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if (LdrOpc == AArch64::LDPXpost || LdrOpc == AArch64::LDPDpost)
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if (BumpSP)
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MIB.addReg(AArch64::SP, RegState::Define);
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MIB.addReg(Reg2, getDefRegState(true))
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@ -908,6 +933,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
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CanEliminateFrame = false;
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}
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DEBUG(dbgs() << "\n");
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// FIXME: Set BigStack if any stack slot references may be out of range.
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// For now, just conservatively guestimate based on unscaled indexing
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