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[X86] Split BT and BTC/BTR/BTS scheduler classes 

llvm-svn: 343233
This commit is contained in:
Simon Pilgrim 2018-09-27 16:24:42 +00:00
parent 06ccc9d998
commit 29cf499bca
11 changed files with 33 additions and 28 deletions
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12
llvm/lib/Target/X86/X86InstrInfo.td
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@ -1818,7 +1818,7 @@ def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
} // SchedRW
let hasSideEffects = 0 in {
let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {
let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB, NotMemoryFoldable;
@ -1842,7 +1842,7 @@ def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
NotMemoryFoldable;
}
let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {
let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
@ -1861,7 +1861,7 @@ def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
Requires<[In64BitMode]>;
}
let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {
let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB, NotMemoryFoldable;
@ -1885,7 +1885,7 @@ def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
NotMemoryFoldable;
}
let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {
let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB;
@ -1908,7 +1908,7 @@ def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
Requires<[In64BitMode]>;
}
let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {
let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB, NotMemoryFoldable;
@ -1932,7 +1932,7 @@ def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
NotMemoryFoldable;
}
let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {
let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),

5
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -161,8 +161,9 @@ def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}
def : WriteRes<WriteLAHFSAHF, [BWPort06]>;
def : WriteRes<WriteBitTest,[BWPort06]>; // Bit Test instrs
def : WriteRes<WriteLAHFSAHF, [BWPort06]>;
def : WriteRes<WriteBitTest, [BWPort06]>; // Bit Test instrs
def : WriteRes<WriteBitTestSet, [BWPort06]>; // Bit Test + Set instrs
// Bit counts.
defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;

5
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -165,8 +165,9 @@ def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}
def : WriteRes<WriteLAHFSAHF, [HWPort06]>;
def : WriteRes<WriteBitTest,[HWPort06]>;
def : WriteRes<WriteLAHFSAHF, [HWPort06]>;
def : WriteRes<WriteBitTest, [HWPort06]>;
def : WriteRes<WriteBitTestSet, [HWPort06]>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on

5
llvm/lib/Target/X86/X86SchedSandyBridge.td
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@ -160,8 +160,9 @@ def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> {
let Latency = 2;
let NumMicroOps = 3;
}
def : WriteRes<WriteLAHFSAHF, [SBPort05]>;
def : WriteRes<WriteBitTest,[SBPort05]>;
def : WriteRes<WriteLAHFSAHF, [SBPort05]>;
def : WriteRes<WriteBitTest, [SBPort05]>;
def : WriteRes<WriteBitTestSet, [SBPort05]>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on

5
llvm/lib/Target/X86/X86SchedSkylakeClient.td
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@ -158,8 +158,9 @@ def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}
def : WriteRes<WriteLAHFSAHF, [SKLPort06]>;
def : WriteRes<WriteBitTest,[SKLPort06]>; //
def : WriteRes<WriteLAHFSAHF, [SKLPort06]>;
def : WriteRes<WriteBitTest, [SKLPort06]>;
def : WriteRes<WriteBitTestSet, [SKLPort06]>;
// Bit counts.
defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;

5
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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@ -159,8 +159,9 @@ def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}
def : WriteRes<WriteLAHFSAHF, [SKXPort06]>;
def : WriteRes<WriteBitTest, [SKXPort06]>; //
def : WriteRes<WriteLAHFSAHF, [SKXPort06]>;
def : WriteRes<WriteBitTest, [SKXPort06]>;
def : WriteRes<WriteBitTestSet, [SKXPort06]>;
// Integer shifts and rotates.
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;

1
llvm/lib/Target/X86/X86Schedule.td
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@ -156,6 +156,7 @@ def WriteSETCC : SchedWrite; // Set register based on condition code.
def WriteSETCCStore : SchedWrite;
def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH.
def WriteBitTest : SchedWrite; // Bit Test - TODO add memory folding support
def WriteBitTestSet : SchedWrite; // Bit Test + Set - TODO add memory folding support
// Integer shifts and rotates.
defm WriteShift : X86SchedWritePair;

3
llvm/lib/Target/X86/X86ScheduleAtom.td
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@ -121,7 +121,8 @@ def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
let Latency = 2;
let ResourceCycles = [2];
}
def : WriteRes<WriteBitTest,[AtomPort01]>;
defm : X86WriteRes<WriteBitTest, [AtomPort01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSet, [AtomPort01], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [AtomPort1]>;

4
llvm/lib/Target/X86/X86ScheduleBtVer2.td
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@ -200,7 +200,9 @@ defm : X86WriteRes<WriteFCMOV, [JFPU0, JFPA], 3, [1,1], 1>; // x87 conditional m
def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;
def : WriteRes<WriteLAHFSAHF, [JALU01]>;
def : WriteRes<WriteBitTest,[JALU01]>;
defm : X86WriteRes<WriteBitTest, [JALU01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSet, [JALU01], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [JALU01]>;

5
llvm/lib/Target/X86/X86ScheduleSLM.td
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@ -134,8 +134,9 @@ def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
// FIXME Latency and NumMicrOps?
let ResourceCycles = [2,1];
}
def : WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01]>;
def : WriteRes<WriteBitTest,[SLM_IEC_RSV01]>;
def : WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01]>;
def : WriteRes<WriteBitTest, [SLM_IEC_RSV01]>;
def : WriteRes<WriteBitTestSet, [SLM_IEC_RSV01]>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on

11
llvm/lib/Target/X86/X86ScheduleZnver1.td
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@ -213,7 +213,9 @@ defm : ZnWriteResPair<WriteCMOV2, [ZnALU], 1>;
def : WriteRes<WriteSETCC, [ZnALU]>;
def : WriteRes<WriteSETCCStore, [ZnALU, ZnAGU]>;
defm : X86WriteRes<WriteLAHFSAHF, [ZnALU], 2, [1], 2>;
def : WriteRes<WriteBitTest,[ZnALU]>;
defm : X86WriteRes<WriteBitTest, [ZnALU], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSet, [ZnALU], 2, [1], 2>;
// Bit counts.
defm : ZnWriteResPair<WriteBSF, [ZnALU], 3>;
@ -715,13 +717,6 @@ def ZnWriteALULat2Ld : SchedWriteRes<[ZnAGU, ZnALU]> {
def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
// BTR BTS BTC.
// r,r,i.
def ZnWriteBTRSC : SchedWriteRes<[ZnALU]> {
let Latency = 2;
let NumMicroOps = 2;
}
def : InstRW<[ZnWriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
// m,r,i.
def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> {
let Latency = 6;