forked from OSchip/llvm-project
Added Skylake client to X86 targets and features
Changes in X86.td: I set features of Intel processors in incremental form: IVB = SNB + X HSW = IVB + X .. I added Skylake client processor and defined it's features FeatureADX was missing on KNL Added some new features to appropriate processors SMAP, IFMA, PREFETCHWT1, VMFUNC and others Differential Revision: http://reviews.llvm.org/D16357 llvm-svn: 258659
This commit is contained in:
Elena Demikhovsky
parent
c077841492
commit
29cde35b43
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@ -805,25 +805,34 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
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Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
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Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
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Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
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Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
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Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
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Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
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Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
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Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
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Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
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Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
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Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
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Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
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Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
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Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
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Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
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// Enable protection keys
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Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
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// AVX512 is only supported if the OS supports the context save for it.
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Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
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Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
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Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
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Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
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Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
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Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
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Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
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Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
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Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
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Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
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Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
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// Enable protection keys
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Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
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bool HasLeafD = MaxLevel >= 0xd &&
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!GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
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@ -125,6 +125,9 @@ def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
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"true",
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"Prefetch with Intent to Write and T1 Hint">;
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def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
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"Enable AVX-512 Doubleword and Quadword Instructions",
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[FeatureAVX512]>;
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@ -137,6 +140,9 @@ def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
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def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
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"Enable AVX-512 Vector Bit Manipulation Instructions",
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[FeatureAVX512]>;
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def FeatureIFMA : SubtargetFeature<"ifma", "HasIFMA", "true",
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"Enable AVX-512 Integer Fused Multiple-Add",
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[FeatureAVX512]>;
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def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
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"Enable protection keys">;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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@ -202,6 +208,20 @@ def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
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"Invalidate Process-Context Identifier">;
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def FeatureVMFUNC : SubtargetFeature<"vmfunc", "HasVMFUNC", "true",
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"VM Functions">;
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def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
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"Supervisor Mode Access Protection">;
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def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
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"Enable Software Guard Extensions">;
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def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
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"Flush A Cache Line Optimized">;
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def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",
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"Enable Persistent Commit">;
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def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
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"Cache Line Write Back">;
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// TODO: This feature ought to be renamed.
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// What it really refers to are CPUs for which certain instructions
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// (which ones besides the example below?) are microcoded.
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@ -365,13 +385,12 @@ def : WestmereProc<"westmere">;
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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def ProcIntelSNB : SubtargetFeature<"snb", "X86ProcFamily", "IntelSNB",
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" Intel SandyBridge Processor", [
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FeatureMMX,
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FeatureAVX,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureSlowUAMem32,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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@ -379,187 +398,125 @@ class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureXSAVEOPT,
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FeatureLAHFSAHF
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]>;
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class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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ProcIntelSNB,
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FeatureSlowBTMem,
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FeatureSlowUAMem32
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]>;
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def : SandyBridgeProc<"sandybridge">;
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def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
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class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureMMX,
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FeatureAVX,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureSlowUAMem32,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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def ProcIntelIVB : SubtargetFeature<"ivb", "X86ProcFamily", "IntelIVB",
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" Intel IvyBridge Processor", [
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ProcIntelSNB,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureLAHFSAHF
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FeatureFSGSBase
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]>;
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class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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ProcIntelIVB,
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FeatureSlowBTMem,
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FeatureSlowUAMem32
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]>;
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def : IvyBridgeProc<"ivybridge">;
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def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
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class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureMMX,
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def ProcIntelHSW : SubtargetFeature<"hsw", "X86ProcFamily", "IntelHSW",
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" Intel Haswell Processor", [
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ProcIntelIVB,
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FeatureAVX2,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureRDRAND,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureLZCNT,
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FeatureMOVBE,
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FeatureINVPCID,
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FeatureVMFUNC,
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FeatureRTM,
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FeatureHLE,
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FeatureSlowIncDec,
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FeatureLAHFSAHF
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FeatureSlowIncDec
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]>;
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class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel,
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[ProcIntelHSW]>;
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def : HaswellProc<"haswell">;
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def : HaswellProc<"core-avx2">; // Legacy alias.
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class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureMMX,
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FeatureAVX2,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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def ProcIntelBDW : SubtargetFeature<"bdw", "X86ProcFamily", "IntelBDW",
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" Intel Broadwell Processor", [
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ProcIntelHSW,
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FeatureADX,
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FeatureRDSEED,
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FeatureSlowIncDec,
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FeatureLAHFSAHF
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FeatureSMAP
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]>;
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class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel,
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[ProcIntelBDW]>;
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def : BroadwellProc<"broadwell">;
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def ProcIntelSKL : SubtargetFeature<"skl", "X86ProcFamily", "IntelSKL",
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" Intel Skylake Client Processor", [
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ProcIntelBDW,
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FeatureMPX,
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FeatureXSAVEC,
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FeatureXSAVES,
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FeatureSGX,
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FeatureCLFLUSHOPT
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]>;
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// FIXME: define SKL model
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class SkylakeClientProc<string Name> : ProcessorModel<Name, HaswellModel,
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[ProcIntelSKL]>;
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def : SkylakeClientProc<"skl">;
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// FIXME: define KNL model
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class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureMMX,
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class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,[
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ProcIntelIVB,
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FeatureAVX512,
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FeatureFXSR,
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FeatureERI,
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FeatureCDI,
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FeaturePFI,
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FeatureCMPXCHG16B,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeaturePREFETCHWT1,
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FeatureADX,
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FeatureRDSEED,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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FeatureSlowIncDec,
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FeatureMPX,
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FeatureLAHFSAHF
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FeatureFMA
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]>;
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def : KnightsLandingProc<"knl">;
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// FIXME: define SKX model
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class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureMMX,
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def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", "IntelSKX",
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" Intel Skylake Server Processor", [
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ProcIntelSKL,
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FeatureAVX512,
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FeatureFXSR,
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FeatureCDI,
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FeatureDQI,
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FeatureBWI,
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FeatureVLX,
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FeaturePKU,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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FeatureADX,
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FeatureRDSEED,
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FeatureSlowIncDec,
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FeatureMPX,
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FeatureXSAVEC,
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FeatureXSAVES,
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FeatureLAHFSAHF
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FeaturePCOMMIT,
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FeatureCLWB
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]>;
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def : SkylakeProc<"skylake">;
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def : SkylakeProc<"skx">; // Legacy alias.
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class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureMMX,
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FeatureAVX512,
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FeatureFXSR,
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FeatureCDI,
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FeatureDQI,
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FeatureBWI,
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FeatureVLX,
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FeaturePKU,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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// FIXME: define SKX model
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class SkylakeServerProc<string Name> : ProcessorModel<Name, HaswellModel,
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[ ProcIntelSKX]>;
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def : SkylakeServerProc<"skylake">;
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def : SkylakeServerProc<"skx">; // Legacy alias.
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def ProcIntelCNL : SubtargetFeature<"cnl", "X86ProcFamily", "IntelCNL",
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" Intel Cannonlake Processor", [
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ProcIntelSKX,
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FeatureVBMI,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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FeatureADX,
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FeatureRDSEED,
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FeatureSlowIncDec,
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FeatureMPX,
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FeatureXSAVEC,
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FeatureXSAVES,
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FeatureLAHFSAHF
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FeatureIFMA,
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FeatureSHA
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]>;
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class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel,
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[ ProcIntelCNL ]>;
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def : CannonlakeProc<"cannonlake">;
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def : CannonlakeProc<"cnl">;
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@ -797,6 +797,8 @@ def HasBMI : Predicate<"Subtarget->hasBMI()">;
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def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
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def HasVBMI : Predicate<"Subtarget->hasVBMI()">,
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AssemblerPredicate<"FeatureVBMI", "AVX-512 VBMI ISA">;
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def HasIFMA : Predicate<"Subtarget->hasIFMA()">,
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AssemblerPredicate<"FeatureIFMA", "AVX-512 IFMA ISA">;
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def HasRTM : Predicate<"Subtarget->hasRTM()">;
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def HasHLE : Predicate<"Subtarget->hasHLE()">;
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def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
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@ -262,6 +262,7 @@ void X86Subtarget::initializeEnvironment() {
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HasBMI = false;
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HasBMI2 = false;
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HasVBMI = false;
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HasIFMA = false;
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HasRTM = false;
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HasHLE = false;
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HasERI = false;
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@ -55,7 +55,8 @@ protected:
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};
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enum X86ProcFamilyEnum {
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Others, IntelAtom, IntelSLM
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Others, IntelAtom, IntelSLM, IntelSNB, IntelIVB, IntelHSW, IntelBDW,
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IntelKNL, IntelSKL, IntelSKX, IntelCNL
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};
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/// X86 processor family: Intel Atom, and others
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@ -137,6 +138,9 @@ protected:
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/// Processor has VBMI instructions.
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bool HasVBMI;
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/// Processor has Integer Fused Multiply Add
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bool HasIFMA;
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/// Processor has RTM instructions.
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bool HasRTM;
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@ -158,6 +162,9 @@ protected:
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/// Processor has LAHF/SAHF instructions.
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bool HasLAHFSAHF;
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/// Processor has Prefetch with intent to Write instruction
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bool HasPFPREFETCHWT1;
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/// True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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@ -229,9 +236,30 @@ protected:
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/// Processor has PKU extenstions
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bool HasPKU;
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/// Processot supports MPX - Memory Protection Extensions
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/// Processor supports MPX - Memory Protection Extensions
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bool HasMPX;
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/// Processor supports Invalidate Process-Context Identifier
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bool HasInvPCId;
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/// Processor has VM Functions
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bool HasVMFUNC;
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/// Processor has Supervisor Mode Access Protection
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bool HasSMAP;
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/// Processor has Software Guard Extensions
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bool HasSGX;
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/// Processor supports Flush Cache Line instruction
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bool HasCLFLUSHOPT;
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/// Processor has Persistent Commit feature
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bool HasPCOMMIT;
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/// Processor supports Cache Line Write Back instruction
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bool HasCLWB;
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/// Use software floating point for code generation.
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bool UseSoftFloat;
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@ -378,6 +406,7 @@ public:
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bool hasBMI() const { return HasBMI; }
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bool hasBMI2() const { return HasBMI2; }
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bool hasVBMI() const { return HasVBMI; }
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bool hasIFMA() const { return HasIFMA; }
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bool hasRTM() const { return HasRTM; }
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bool hasHLE() const { return HasHLE; }
|
||||
bool hasADX() const { return HasADX; }
|
||||
|
|
|
|||
|
|
@ -214,31 +214,31 @@ define i64 @test_cmp_b_512(<64 x i8> %a0, <64 x i8> %a1) {
|
|||
; AVX512F-32-NEXT: vpcmpltb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpleb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpunordb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpneqb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnltb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnleb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpordb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, (%esp)
|
||||
; AVX512F-32-NEXT: addl (%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: addl $68, %esp
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res0 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 -1)
|
||||
|
|
@ -303,31 +303,31 @@ define i64 @test_mask_cmp_b_512(<64 x i8> %a0, <64 x i8> %a1, i64 %mask) {
|
|||
; AVX512F-32-NEXT: vpcmpltb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpleb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpunordb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpneqb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnltb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnleb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpordb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: addl $68, %esp
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res0 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 %mask)
|
||||
|
|
@ -390,31 +390,31 @@ define i64 @test_ucmp_b_512(<64 x i8> %a0, <64 x i8> %a1) {
|
|||
; AVX512F-32-NEXT: vpcmpltub %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpleub %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpunordub %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnequb %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnltub %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpordub %zmm1, %zmm0, %k0
|
||||
; AVX512F-32-NEXT: kmovq %k0, (%esp)
|
||||
; AVX512F-32-NEXT: addl (%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: addl $68, %esp
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res0 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 -1)
|
||||
|
|
@ -479,31 +479,31 @@ define i64 @test_mask_x86_avx512_ucmp_b_512(<64 x i8> %a0, <64 x i8> %a1, i64 %m
|
|||
; AVX512F-32-NEXT: vpcmpltub %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpleub %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpunordub %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnequb %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnltub %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpnleub %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: vpcmpordub %zmm1, %zmm0, %k0 {%k1}
|
||||
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
|
||||
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: adcl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: adcxl {{[0-9]+}}(%esp), %edx
|
||||
; AVX512F-32-NEXT: addl $68, %esp
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res0 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 %mask)
|
||||
|
|
@ -2879,6 +2879,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psrl_w_512(<32 x i16> %x0, <8 x i16>
|
|||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm2, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm3, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrl_w_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsrlw %xmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512F-32-NEXT: vpsrlw %xmm1, %zmm0, %zmm3 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsrlw %xmm1, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm2, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm3, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psrl.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psrl.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 -1)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psrl.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)
|
||||
|
|
@ -2899,6 +2909,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psrl_wi_512(<32 x i16> %x0, i8 %x1, <
|
|||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrl_wi_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsrlw $3, %zmm0, %zmm1 {%k1}
|
||||
; AVX512F-32-NEXT: vpsrlw $3, %zmm0, %zmm2 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsrlw $3, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm2, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psrl.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psrl.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psrl.wi.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)
|
||||
|
|
@ -2919,6 +2939,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psrlv32hi(<32 x i16> %x0, <32 x i16>
|
|||
; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrlv32hi:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsrlvw %zmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512F-32-NEXT: vpsrlvw %zmm1, %zmm0, %zmm3 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psrlv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psrlv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psrlv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -2939,6 +2969,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psra_w_512(<32 x i16> %x0, <8 x i16>
|
|||
; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psra_w_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsraw %xmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512F-32-NEXT: vpsraw %xmm1, %zmm0, %zmm3 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsraw %xmm1, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psra.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psra.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psra.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -2959,6 +2999,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psra_wi_512(<32 x i16> %x0, i8 %x1, <
|
|||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psra_wi_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsraw $3, %zmm0, %zmm1 {%k1}
|
||||
; AVX512F-32-NEXT: vpsraw $3, %zmm0, %zmm2 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsraw $3, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psra.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psra.wi.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psra.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -2979,6 +3029,16 @@ define <32 x i16>@test_int_x86_avx512_mask_pshufh_w_512(<32 x i16> %x0, i8 %x1,
|
|||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_pshufh_w_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpshufhw $3, %zmm0, %zmm1 {%k1}
|
||||
; AVX512F-32-NEXT: vpshufhw $3, %zmm0, %zmm2 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpshufhw $3, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.pshufh.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.pshufh.w.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.pshufh.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -2992,13 +3052,23 @@ declare <32 x i16> @llvm.x86.avx512.mask.pshufl.w.512(<32 x i16>, i8, <32 x i16>
|
|||
define <32 x i16>@test_int_x86_avx512_mask_pshufl_w_512(<32 x i16> %x0, i8 %x1, <32 x i16> %x2, i32 %x3) {
|
||||
; AVX512BW-LABEL: test_int_x86_avx512_mask_pshufl_w_512:
|
||||
; AVX512BW: ## BB#0:
|
||||
; AVX512BW-NEXT: kmovd %esi, %k1
|
||||
; AVX512BW-NEXT: vpshuflw $3, %zmm0, %zmm1 {%k1}
|
||||
; AVX512BW-NEXT: vpshuflw $3, %zmm0, %zmm2 {%k1} {z}
|
||||
; AVX512BW-NEXT: vpshuflw $3, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
; AVX512BW-NEXT: kmovd %esi, %k1
|
||||
; AVX512BW-NEXT: vpshuflw $3, %zmm0, %zmm1 {%k1}
|
||||
; AVX512BW-NEXT: vpshuflw $3, %zmm0, %zmm2 {%k1} {z}
|
||||
; AVX512BW-NEXT: vpshuflw $3, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_pshufl_w_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpshuflw $3, %zmm0, %zmm1 {%k1}
|
||||
; AVX512F-32-NEXT: vpshuflw $3, %zmm0, %zmm2 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpshuflw $3, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.pshufl.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.pshufl.w.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.pshufl.w.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -3019,6 +3089,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psrav32_hi(<32 x i16> %x0, <32 x i16>
|
|||
; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psrav32_hi:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsravw %zmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512F-32-NEXT: vpsravw %zmm1, %zmm0, %zmm3 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsravw %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psrav32.hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psrav32.hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psrav32.hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -3039,6 +3119,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psll_w_512(<32 x i16> %x0, <8 x i16>
|
|||
; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psll_w_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsllw %xmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512F-32-NEXT: vpsllw %xmm1, %zmm0, %zmm3 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsllw %xmm1, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psll.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psll.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psll.w.512(<32 x i16> %x0, <8 x i16> %x1, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -3059,6 +3149,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psll_wi_512(<32 x i16> %x0, i8 %x1, <
|
|||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psll_wi_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsllw $3, %zmm0, %zmm1 {%k1}
|
||||
; AVX512F-32-NEXT: vpsllw $3, %zmm0, %zmm2 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsllw $3, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psll.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psll.wi.512(<32 x i16> %x0, i8 3, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psll.wi.512(<32 x i16> %x0, i8 3, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -3079,6 +3179,16 @@ define <32 x i16>@test_int_x86_avx512_mask_psllv32hi(<32 x i16> %x0, <32 x i16>
|
|||
; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_psllv32hi:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpsllvw %zmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512F-32-NEXT: vpsllvw %zmm1, %zmm0, %zmm3 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.psllv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.psllv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.psllv32hi(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
|
||||
|
|
@ -3152,13 +3262,23 @@ declare <32 x i16> @llvm.x86.avx512.mask.pmovzxb.w.512(<32 x i8>, <32 x i16>, i3
|
|||
define <32 x i16>@test_int_x86_avx512_mask_pmovzxb_w_512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2) {
|
||||
; AVX512BW-LABEL: test_int_x86_avx512_mask_pmovzxb_w_512:
|
||||
; AVX512BW: ## BB#0:
|
||||
; AVX512BW-NEXT: kmovd %edi, %k1
|
||||
; AVX512BW-NEXT: vpmovzxbw %ymm0, %zmm1 {%k1}
|
||||
; AVX512BW-NEXT: vpmovzxbw %ymm0, %zmm2 {%k1} {z}
|
||||
; AVX512BW-NEXT: vpmovzxbw %ymm0, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
; AVX512BW-NEXT: kmovd %edi, %k1
|
||||
; AVX512BW-NEXT: vpmovzxbw %ymm0, %zmm1 {%k1}
|
||||
; AVX512BW-NEXT: vpmovzxbw %ymm0, %zmm2 {%k1} {z}
|
||||
; AVX512BW-NEXT: vpmovzxbw %ymm0, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmovzxb_w_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpmovzxbw %ymm0, %zmm1 {%k1}
|
||||
; AVX512F-32-NEXT: vpmovzxbw %ymm0, %zmm2 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpmovzxbw %ymm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.pmovzxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.pmovzxb.w.512(<32 x i8> %x0, <32 x i16> zeroinitializer, i32 %x2)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.pmovzxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 -1)
|
||||
|
|
@ -3172,13 +3292,23 @@ declare <32 x i16> @llvm.x86.avx512.mask.pmovsxb.w.512(<32 x i8>, <32 x i16>, i3
|
|||
define <32 x i16>@test_int_x86_avx512_mask_pmovsxb_w_512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2) {
|
||||
; AVX512BW-LABEL: test_int_x86_avx512_mask_pmovsxb_w_512:
|
||||
; AVX512BW: ## BB#0:
|
||||
; AVX512BW-NEXT: kmovd %edi, %k1
|
||||
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm1 {%k1}
|
||||
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm2 {%k1} {z}
|
||||
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
; AVX512BW-NEXT: kmovd %edi, %k1
|
||||
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm1 {%k1}
|
||||
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm2 {%k1} {z}
|
||||
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm0
|
||||
; AVX512BW-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmovsxb_w_512:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
||||
; AVX512F-32-NEXT: vpmovsxbw %ymm0, %zmm1 {%k1}
|
||||
; AVX512F-32-NEXT: vpmovsxbw %ymm0, %zmm2 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpmovsxbw %ymm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm2, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.pmovsxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 %x2)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.pmovsxb.w.512(<32 x i8> %x0, <32 x i16> zeroinitializer, i32 %x2)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.pmovsxb.w.512(<32 x i8> %x0, <32 x i16> %x1, i32 -1)
|
||||
|
|
@ -3192,13 +3322,23 @@ declare <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16>, <32 x i16>,
|
|||
define <32 x i16>@test_int_x86_avx512_mask_permvar_hi_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
|
||||
; AVX512BW-LABEL: test_int_x86_avx512_mask_permvar_hi_512:
|
||||
; AVX512BW: ## BB#0:
|
||||
; AVX512BW-NEXT: kmovd %edi, %k1
|
||||
; AVX512BW-NEXT: vpermw %zmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512BW-NEXT: vpermw %zmm1, %zmm0, %zmm3 {%k1} {z}
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; AVX512BW-NEXT: vpermw %zmm1, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm1
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; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
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; AVX512BW-NEXT: retq
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; AVX512BW-NEXT: kmovd %edi, %k1
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; AVX512BW-NEXT: vpermw %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512BW-NEXT: vpermw %zmm1, %zmm0, %zmm3 {%k1} {z}
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||||
; AVX512BW-NEXT: vpermw %zmm1, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm1
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; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
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; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512F-32-LABEL: test_int_x86_avx512_mask_permvar_hi_512:
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; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
|
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; AVX512F-32-NEXT: vpermw %zmm1, %zmm0, %zmm2 {%k1}
|
||||
; AVX512F-32-NEXT: vpermw %zmm1, %zmm0, %zmm3 {%k1} {z}
|
||||
; AVX512F-32-NEXT: vpermw %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm1
|
||||
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
|
||||
; AVX512F-32-NEXT: retl
|
||||
%res = call <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
|
||||
%res1 = call <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> zeroinitializer, i32 %x3)
|
||||
%res2 = call <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue