forked from OSchip/llvm-project
[SimplifyCFG] simplifyUnreachable(): fix handling of degenerate same-destination conditional branch
One would hope that it would have been already canonicalized into an unconditional branch, but that isn't really guaranteed to happen with SimplifyCFG's visitation order.
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@ -4683,16 +4683,18 @@ bool SimplifyCFGOpt::simplifyUnreachable(UnreachableInst *UI) {
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Instruction *TI = Predecessor->getTerminator();
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IRBuilder<> Builder(TI);
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if (auto *BI = dyn_cast<BranchInst>(TI)) {
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if (BI->isUnconditional()) {
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assert(BI->getSuccessor(0) == BB && "Incorrect CFG");
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// We could either have a proper unconditional branch,
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// or a degenerate conditional branch with matching destinations.
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if (all_of(BI->successors(),
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[BB](auto *Successor) { return Successor == BB; })) {
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new UnreachableInst(TI->getContext(), TI);
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TI->eraseFromParent();
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Changed = true;
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} else {
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assert(BI->isConditional() && "Can't get here with an uncond branch.");
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Value* Cond = BI->getCondition();
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// assert(BI->getSuccessor(0) != BI->getSuccessor(1) &&
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// "Same-destination conditional branch instruction was "
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// "already canonicalized into an unconditional branch.");
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assert(BI->getSuccessor(0) != BI->getSuccessor(1) &&
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"The destinations are guaranteed to be different here.");
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if (BI->getSuccessor(0) == BB) {
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Builder.CreateAssumption(Builder.CreateNot(Cond));
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Builder.CreateBr(BI->getSuccessor(1));
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@ -1,5 +1,5 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck %s
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; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
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@global = external global i16, align 1
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@global.1 = external global i16, align 1
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@ -11,14 +11,6 @@ define void @widget() {
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; CHECK-NEXT: [[I:%.*]] = load i16, i16* @global, align 1
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; CHECK-NEXT: [[I13:%.*]] = icmp ne i16 [[I]], 0
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; CHECK-NEXT: call void @llvm.assume(i1 [[I13]])
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; CHECK-NEXT: [[I17:%.*]] = load i16, i16* @global, align 1
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; CHECK-NEXT: [[I18:%.*]] = sdiv i16 2, [[I17]]
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; CHECK-NEXT: [[I19:%.*]] = icmp ne i16 [[I18]], 0
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; CHECK-NEXT: [[I20:%.*]] = zext i1 [[I19]] to i16
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; CHECK-NEXT: [[I21:%.*]] = load i16, i16* @global.1, align 1
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[I19]], i16 [[I20]], i16 [[I21]]
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; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[I19]], true
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; CHECK-NEXT: call void @llvm.assume(i1 [[TMP0]])
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; CHECK-NEXT: unreachable
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;
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bb:
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