forked from OSchip/llvm-project
parent
76326b0540
commit
299022d514
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@ -364,6 +364,25 @@ void LiveIntervals::printRegName(unsigned reg) const {
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std::cerr << "%reg" << reg;
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}
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/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
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/// two addr elimination.
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static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
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const TargetInstrInfo *TII) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO1 = MI->getOperand(i);
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if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
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for (unsigned j = i+1; j < e; ++j) {
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MachineOperand &MO2 = MI->getOperand(j);
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if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
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TII->getOperandConstraint(MI->getOpcode(), j,
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TargetInstrInfo::TIED_TO) == (int)i)
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return true;
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}
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}
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}
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return false;
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}
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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MachineBasicBlock::iterator mi,
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unsigned MIIdx,
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@ -453,13 +472,9 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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} else {
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// If this is the second time we see a virtual register definition, it
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// must be due to phi elimination or two addr elimination. If this is
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// the result of two address elimination, then the vreg is the first
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// operand, and is a def-and-use.
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if (mi->getOperand(0).isRegister() &&
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mi->getOperand(0).getReg() == interval.reg &&
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mi->getNumOperands() > 1 && mi->getOperand(1).isRegister() &&
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mi->getOperand(1).getReg() == interval.reg &&
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mi->getOperand(0).isDef() && mi->getOperand(1).isUse()) {
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// the result of two address elimination, then the vreg is one of the
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// def-and-use register operand.
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if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
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// If this is a two-address definition, then we have already processed
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// the live range. The only problem is that we didn't realize there
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// are actually two values in the live interval. Because of this we
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