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Proper check for two-addressness. 

llvm-svn: 31408
This commit is contained in:
Evan Cheng 2006-11-03 03:04:46 +00:00
parent 76326b0540
commit 299022d514
1 changed files with 22 additions and 7 deletions
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29
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -364,6 +364,25 @@ void LiveIntervals::printRegName(unsigned reg) const {
std::cerr << "%reg" << reg; std::cerr << "%reg" << reg;
} }
/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
/// two addr elimination.
static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
const TargetInstrInfo *TII) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO1 = MI->getOperand(i);
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
for (unsigned j = i+1; j < e; ++j) {
MachineOperand &MO2 = MI->getOperand(j);
if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
TII->getOperandConstraint(MI->getOpcode(), j,
TargetInstrInfo::TIED_TO) == (int)i)
return true;
}
}
}
return false;
}
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineBasicBlock::iterator mi, MachineBasicBlock::iterator mi,
unsigned MIIdx, unsigned MIIdx,
@ -453,13 +472,9 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
} else { } else {
// If this is the second time we see a virtual register definition, it // If this is the second time we see a virtual register definition, it
// must be due to phi elimination or two addr elimination. If this is // must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is the first // the result of two address elimination, then the vreg is one of the
// operand, and is a def-and-use. // def-and-use register operand.
if (mi->getOperand(0).isRegister() && if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
mi->getOperand(0).getReg() == interval.reg &&
mi->getNumOperands() > 1 && mi->getOperand(1).isRegister() &&
mi->getOperand(1).getReg() == interval.reg &&
mi->getOperand(0).isDef() && mi->getOperand(1).isUse()) {
// If this is a two-address definition, then we have already processed // If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there // the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we // are actually two values in the live interval. Because of this we