forked from OSchip/llvm-project
[NFC][regalloc] Use MCRegister instead of unsigned in InterferenceCache
Also changed users of APIs. Differential Revision: https://reviews.llvm.org/D88930
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@ -60,8 +60,8 @@ void InterferenceCache::init(MachineFunction *mf,
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Entries[i].clear(mf, indexes, lis);
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}
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InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
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unsigned E = PhysRegEntries[PhysReg];
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InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) {
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unsigned char E = PhysRegEntries[PhysReg.id()];
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if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
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if (!Entries[E].valid(LIUArray, TRI))
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Entries[E].revalidate(LIUArray, TRI);
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@ -97,7 +97,7 @@ void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
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RegUnits[i].VirtTag = LIUArray[*Units].getTag();
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}
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void InterferenceCache::Entry::reset(unsigned physReg,
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void InterferenceCache::Entry::reset(MCRegister physReg,
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LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI,
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const MachineFunction *MF) {
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@ -44,7 +44,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
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/// of PhysReg in all basic blocks.
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class Entry {
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/// PhysReg - The register currently represented.
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unsigned PhysReg = 0;
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MCRegister PhysReg = 0;
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/// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
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/// change.
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@ -102,13 +102,13 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
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void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
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assert(!hasRefs() && "Cannot clear cache entry with references");
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PhysReg = 0;
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PhysReg = MCRegister::NoRegister;
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MF = mf;
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Indexes = indexes;
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LIS = lis;
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}
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unsigned getPhysReg() const { return PhysReg; }
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MCRegister getPhysReg() const { return PhysReg; }
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void addRef(int Delta) { RefCount += Delta; }
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@ -120,10 +120,8 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
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bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
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/// reset - Initialize entry to represent physReg's aliases.
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void reset(unsigned physReg,
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LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI,
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const MachineFunction *MF);
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void reset(MCRegister physReg, LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI, const MachineFunction *MF);
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/// get - Return an up to date BlockInterference.
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BlockInterference *get(unsigned MBBNum) {
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@ -154,7 +152,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
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Entry Entries[CacheEntries];
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// get - Get a valid entry for PhysReg.
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Entry *get(unsigned PhysReg);
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Entry *get(MCRegister PhysReg);
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public:
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InterferenceCache() = default;
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@ -207,11 +205,11 @@ public:
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~Cursor() { setEntry(nullptr); }
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/// setPhysReg - Point this cursor to PhysReg's interference.
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void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) {
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void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) {
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// Release reference before getting a new one. That guarantees we can
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// actually have CacheEntries live cursors.
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setEntry(nullptr);
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if (PhysReg)
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if (PhysReg.isValid())
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setEntry(Cache.get(PhysReg));
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}
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@ -361,7 +361,7 @@ class RAGreedy : public MachineFunctionPass,
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BitVector LiveBundles;
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SmallVector<unsigned, 8> ActiveBlocks;
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void reset(InterferenceCache &Cache, unsigned Reg) {
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void reset(InterferenceCache &Cache, MCRegister Reg) {
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PhysReg = Reg;
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IntvIdx = 0;
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Intf.setPhysReg(Cache, Reg);
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@ -1372,7 +1372,7 @@ bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
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return false;
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// Compact regions don't correspond to any physreg.
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Cand.reset(IntfCache, 0);
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Cand.reset(IntfCache, MCRegister::NoRegister);
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LLVM_DEBUG(dbgs() << "Compact region bundles");
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