forked from OSchip/llvm-project
initial hack at splitting the x86-64 calling convention info out from the
mechanics that process it. I'm still not happy with this, but it's a step in the right direction. llvm-svn: 34631
This commit is contained in:
Chris Lattner
parent
862ee00550
commit
294780829a
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@ -833,7 +833,7 @@ SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
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// Return the new list of results.
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return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
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&ArgValues[0], ArgValues.size());
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&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
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}
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SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
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@ -1058,64 +1058,265 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
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// X86-64 C Calling Convention implementation
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//===----------------------------------------------------------------------===//
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/// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified
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/// type should be passed. If it is through stack, returns the size of the stack
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/// slot; if it is through integer or XMM register, returns the number of
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/// integer or XMM registers are needed.
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static void
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HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT,
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unsigned NumIntRegs, unsigned NumXMMRegs,
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unsigned &ObjSize, unsigned &ObjIntRegs,
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unsigned &ObjXMMRegs) {
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ObjSize = 0;
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ObjIntRegs = 0;
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ObjXMMRegs = 0;
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class CallingConvState {
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uint32_t UsedRegs[(X86::NUM_TARGET_REGS+31)/32];
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unsigned StackOffset;
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const MRegisterInfo &MRI;
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public:
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CallingConvState(const MRegisterInfo &mri) : MRI(mri) {
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// No stack is used.
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StackOffset = 0;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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if (NumIntRegs < 6)
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ObjIntRegs = 1;
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else {
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switch (ObjectVT) {
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default: break;
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case MVT::i8: ObjSize = 1; break;
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case MVT::i16: ObjSize = 2; break;
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case MVT::i32: ObjSize = 4; break;
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case MVT::i64: ObjSize = 8; break;
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}
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}
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break;
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case MVT::f32:
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case MVT::f64:
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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if (NumXMMRegs < 8)
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ObjXMMRegs = 1;
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else {
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switch (ObjectVT) {
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default: break;
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case MVT::f32: ObjSize = 4; break;
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case MVT::f64: ObjSize = 8; break;
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64: ObjSize = 16; break;
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}
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break;
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UsedRegs.resize(MRI.getNumRegs());
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// No registers are used.
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memset(UsedRegs, 0, sizeof(UsedRegs));
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}
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unsigned getNextStackOffset() const { return StackOffset; }
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/// isAllocated - Return true if the specified register (or an alias) is
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/// allocated.
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bool isAllocated(unsigned Reg) const {
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return UsedRegs[Reg/32] & (1 << (Reg&31));
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}
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/// getFirstUnallocated - Return the first unallocated register in the set, or
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/// NumRegs if they are all allocated.
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unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
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for (unsigned i = 0; i != NumRegs; ++i)
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if (!isAllocated(Regs[i]))
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return i;
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return NumRegs;
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}
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/// AllocateReg - Attempt to allocate one of the specified registers. If none
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/// are available, return zero. Otherwise, return the first one available,
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/// marking it and any aliases as allocated.
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unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
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unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
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if (FirstUnalloc == NumRegs)
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return 0; // Didn't find the reg.
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// Mark the register and any aliases as allocated.
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unsigned Reg = Regs[FirstUnalloc];
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MarkAllocated(Reg);
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if (const unsigned *RegAliases = MRI.getAliasSet(Reg))
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for (; *RegAliases; ++RegAliases)
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MarkAllocated(*RegAliases);
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return Reg;
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}
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/// AllocateStack - Allocate a chunk of stack space with the specified size
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/// and alignment.
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unsigned AllocateStack(unsigned Size, unsigned Align) {
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assert(Align && ((Align-1) & Align) == 0); // Align is power of 2.
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StackOffset = ((StackOffset + Align-1) & ~(Align-1));
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unsigned Result = StackOffset;
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StackOffset += Size;
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return Result;
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}
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private:
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void MarkAllocated(unsigned Reg) {
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UsedRegs[Reg/32] |= 1 << (Reg&31);
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}
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};
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/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
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template<typename Client, typename DataTy>
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static void X86_64_CCC_AssignArgument(Client &C, CallingConvState &State,
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MVT::ValueType ArgVT, unsigned ArgFlags,
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DataTy Data) {
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MVT::ValueType LocVT = ArgVT;
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unsigned ExtendType = ISD::ANY_EXTEND;
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// Promote the integer to 32 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (ArgVT == MVT::i8 || ArgVT == MVT::i16) {
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LocVT = MVT::i32;
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ExtendType = (ArgFlags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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}
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// If this is a 32-bit value, assign to a 32-bit register if any are
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// available.
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if (LocVT == MVT::i32) {
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static const unsigned GPR32ArgRegs[] = {
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X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
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};
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if (unsigned Reg = State.AllocateReg(GPR32ArgRegs, 6)) {
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C.AssignToReg(Data, Reg, ArgVT, LocVT, ExtendType);
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return;
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}
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}
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// If this is a 64-bit value, assign to a 64-bit register if any are
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// available.
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if (LocVT == MVT::i64) {
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static const unsigned GPR64ArgRegs[] = {
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X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
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};
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if (unsigned Reg = State.AllocateReg(GPR64ArgRegs, 6)) {
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C.AssignToReg(Data, Reg, ArgVT, LocVT, ExtendType);
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return;
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}
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}
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// If this is a FP or vector type, assign to an XMM reg if any are
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// available.
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if (MVT::isVector(LocVT) || MVT::isFloatingPoint(LocVT)) {
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static const unsigned XMMArgRegs[] = {
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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};
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if (unsigned Reg = State.AllocateReg(XMMArgRegs, 8)) {
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C.AssignToReg(Data, Reg, ArgVT, LocVT, ExtendType);
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return;
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}
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}
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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if (LocVT == MVT::i32 || LocVT == MVT::i64 ||
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LocVT == MVT::f32 || LocVT == MVT::f64) {
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unsigned Offset = State.AllocateStack(8, 8);
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C.AssignToStack(Data, Offset, ArgVT, LocVT, ExtendType);
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return;
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}
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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if (MVT::isVector(LocVT)) {
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unsigned Offset = State.AllocateStack(16, 16);
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C.AssignToStack(Data, Offset, ArgVT, LocVT, ExtendType);
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return;
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}
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assert(0 && "Unknown argument type!");
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}
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class LowerArgumentsClient {
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SelectionDAG &DAG;
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X86TargetLowering &TLI;
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SmallVector<SDOperand, 8> &ArgValues;
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SDOperand Chain;
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public:
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LowerArgumentsClient(SelectionDAG &dag, X86TargetLowering &tli,
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SmallVector<SDOperand, 8> &argvalues,
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SDOperand chain)
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: DAG(dag), TLI(tli), ArgValues(argvalues), Chain(chain) {
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}
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void AssignToReg(SDOperand Arg, unsigned RegNo,
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MVT::ValueType ArgVT, MVT::ValueType RegVT,
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unsigned ExtendType) {
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TargetRegisterClass *RC = NULL;
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if (RegVT == MVT::i32)
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RC = X86::GR32RegisterClass;
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else if (RegVT == MVT::i64)
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RC = X86::GR64RegisterClass;
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else if (RegVT == MVT::f32)
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RC = X86::FR32RegisterClass;
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else if (RegVT == MVT::f64)
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RC = X86::FR64RegisterClass;
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else {
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RC = X86::VR128RegisterClass;
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}
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SDOperand ArgValue = DAG.getCopyFromReg(Chain, RegNo, RegVT);
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AddLiveIn(DAG.getMachineFunction(), RegNo, RC);
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// If this is an 8 or 16-bit value, it is really passed promoted to 32
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (ArgVT < RegVT) {
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if (ExtendType == ISD::SIGN_EXTEND) {
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ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
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DAG.getValueType(ArgVT));
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} else if (ExtendType == ISD::ZERO_EXTEND) {
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ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
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DAG.getValueType(ArgVT));
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}
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ArgValue = DAG.getNode(ISD::TRUNCATE, ArgVT, ArgValue);
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}
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ArgValues.push_back(ArgValue);
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}
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void AssignToStack(SDOperand Arg, unsigned Offset,
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MVT::ValueType ArgVT, MVT::ValueType DestVT,
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unsigned ExtendType) {
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// Create the SelectionDAG nodes corresponding to a load from this
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// parameter.
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(ArgVT)/8, Offset);
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SDOperand FIN = DAG.getFrameIndex(FI, TLI.getPointerTy());
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ArgValues.push_back(DAG.getLoad(ArgVT, Chain, FIN, NULL, 0));
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}
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};
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class LowerCallArgumentsClient {
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SelectionDAG &DAG;
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X86TargetLowering &TLI;
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SmallVector<std::pair<unsigned, SDOperand>, 8> &RegsToPass;
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SmallVector<SDOperand, 8> &MemOpChains;
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SDOperand Chain;
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SDOperand StackPtr;
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public:
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LowerCallArgumentsClient(SelectionDAG &dag, X86TargetLowering &tli,
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SmallVector<std::pair<unsigned, SDOperand>, 8> &rtp,
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SmallVector<SDOperand, 8> &moc,
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SDOperand chain)
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: DAG(dag), TLI(tli), RegsToPass(rtp), MemOpChains(moc), Chain(chain) {
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}
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void AssignToReg(SDOperand Arg, unsigned RegNo,
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MVT::ValueType ArgVT, MVT::ValueType RegVT,
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unsigned ExtendType) {
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// If the argument has to be extended somehow before being passed, do so.
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if (ArgVT < RegVT)
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Arg = DAG.getNode(ExtendType, RegVT, Arg);
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RegsToPass.push_back(std::make_pair(RegNo, Arg));
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}
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void AssignToStack(SDOperand Arg, unsigned Offset,
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MVT::ValueType ArgVT, MVT::ValueType DestVT,
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unsigned ExtendType) {
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// If the argument has to be extended somehow before being stored, do so.
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if (ArgVT < DestVT)
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Arg = DAG.getNode(ExtendType, DestVT, Arg);
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SDOperand SP = getSP();
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SDOperand PtrOff = DAG.getConstant(Offset, SP.getValueType());
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PtrOff = DAG.getNode(ISD::ADD, SP.getValueType(), SP, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
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}
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private:
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SDOperand getSP() {
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if (StackPtr.Val == 0) {
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MVT::ValueType PtrTy = TLI.getPointerTy();
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StackPtr = DAG.getRegister(TLI.getStackPtrReg(), PtrTy);
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}
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return StackPtr;
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}
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};
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class EmptyArgumentsClient {
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public:
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EmptyArgumentsClient() {}
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void AssignToReg(SDOperand Arg, unsigned RegNo,
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MVT::ValueType ArgVT, MVT::ValueType RegVT,
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unsigned ExtendType) {
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}
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void AssignToStack(SDOperand Arg, unsigned Offset,
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MVT::ValueType ArgVT, MVT::ValueType DestVT,
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unsigned ExtendType) {
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}
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};
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SDOperand
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X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues() - 1;
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@ -1123,23 +1324,7 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SDOperand Root = Op.getOperand(0);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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SmallVector<SDOperand, 8> ArgValues;
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// Add DAG nodes to load the arguments... On entry to a function on the X86,
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// the stack frame looks like this:
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//
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// [RSP] -- return address
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// [RSP + 8] -- first nonreg argument (leftmost lexically)
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// [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size
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// ...
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//
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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unsigned NumIntRegs = 0; // Int regs used for parameter passing.
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unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
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static const unsigned GPR32ArgRegs[] = {
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X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
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};
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static const unsigned GPR64ArgRegs[] = {
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X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
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};
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@ -1148,105 +1333,33 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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};
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
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SmallVector<SDOperand, 8> ArgValues;
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CallingConvState CCState(*getTargetMachine().getRegisterInfo());
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LowerArgumentsClient Client(DAG, *this, ArgValues, Root);
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for (unsigned i = 0; i != NumArgs; ++i) {
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MVT::ValueType ArgVT = Op.getValue(i).getValueType();
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unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
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unsigned ArgIncrement = 8;
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unsigned ObjSize = 0;
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unsigned ObjIntRegs = 0;
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unsigned ObjXMMRegs = 0;
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// FIXME: __int128 and long double support?
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HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
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ObjSize, ObjIntRegs, ObjXMMRegs);
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if (ObjSize > 8)
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ArgIncrement = ObjSize;
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unsigned Reg = 0;
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SDOperand ArgValue;
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if (ObjIntRegs || ObjXMMRegs) {
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64: {
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TargetRegisterClass *RC = NULL;
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switch (ObjectVT) {
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default: assert(0 && "Unknown integer VT!");
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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RC = X86::GR32RegisterClass;
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Reg = GPR32ArgRegs[NumIntRegs];
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ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
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break;
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case MVT::i64:
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RC = X86::GR64RegisterClass;
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Reg = GPR64ArgRegs[NumIntRegs];
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ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i64);
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break;
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}
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Reg = AddLiveIn(MF, Reg, RC);
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// If this is an 8 or 16-bit value, it is really passed promoted to 32
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (ObjectVT == MVT::i8 || ObjectVT == MVT::i16) {
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// FIXME: FORMAL_ARGUMENTS can't currently distinguish between an
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// argument with undefined high bits, so we can't insert a assertzext
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// yet.
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if (ArgFlags & 1) {
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unsigned ExtOpc = (ArgFlags & 1) ? ISD::AssertSext :ISD::AssertZext;
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ArgValue = DAG.getNode(ExtOpc, MVT::i32, ArgValue,
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DAG.getValueType(ObjectVT));
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}
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ArgValue = DAG.getNode(ISD::TRUNCATE, ObjectVT, ArgValue);
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}
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break;
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}
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case MVT::f32:
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case MVT::f64:
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
|
||||
case MVT::v2f64: {
|
||||
TargetRegisterClass *RC= (ObjectVT == MVT::f32) ?
|
||||
X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ?
|
||||
X86::FR64RegisterClass : X86::VR128RegisterClass);
|
||||
Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC);
|
||||
ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
|
||||
break;
|
||||
}
|
||||
}
|
||||
NumIntRegs += ObjIntRegs;
|
||||
NumXMMRegs += ObjXMMRegs;
|
||||
} else if (ObjSize) {
|
||||
// XMM arguments have to be aligned on 16-byte boundary.
|
||||
if (ObjSize == 16)
|
||||
ArgOffset = ((ArgOffset + 15) / 16) * 16;
|
||||
// Create the SelectionDAG nodes corresponding to a load from this
|
||||
// parameter.
|
||||
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
|
||||
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
|
||||
ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
|
||||
ArgOffset += ArgIncrement; // Move on to the next argument.
|
||||
}
|
||||
|
||||
ArgValues.push_back(ArgValue);
|
||||
X86_64_CCC_AssignArgument(Client, CCState, ArgVT, ArgFlags, SDOperand());
|
||||
}
|
||||
|
||||
unsigned StackSize = CCState.getNextStackOffset();
|
||||
|
||||
// If the function takes variable number of arguments, make a frame index for
|
||||
// the start of the first vararg value... for expansion of llvm.va_start.
|
||||
if (isVarArg) {
|
||||
unsigned NumIntRegs = CCState.getFirstUnallocated(GPR64ArgRegs, 6);
|
||||
unsigned NumXMMRegs = CCState.getFirstUnallocated(XMMArgRegs, 8);
|
||||
|
||||
// For X86-64, if there are vararg parameters that are passed via
|
||||
// registers, then we must store them to their spots on the stack so they
|
||||
// may be loaded by deferencing the result of va_next.
|
||||
VarArgsGPOffset = NumIntRegs * 8;
|
||||
VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
|
||||
VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
|
||||
VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
|
||||
RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
|
||||
|
||||
// Store the integer parameter registers.
|
||||
|
|
@ -1285,11 +1398,11 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
|
|||
|
||||
ReturnAddrIndex = 0; // No return address slot generated yet.
|
||||
BytesToPopOnReturn = 0; // Callee pops nothing.
|
||||
BytesCallerReserves = ArgOffset;
|
||||
BytesCallerReserves = StackSize;
|
||||
|
||||
// Return the new list of results.
|
||||
return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
|
||||
&ArgValues[0], ArgValues.size());
|
||||
&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
|
||||
}
|
||||
|
||||
SDOperand
|
||||
|
|
@ -1303,127 +1416,36 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
|||
|
||||
// Count how many bytes are to be pushed on the stack.
|
||||
unsigned NumBytes = 0;
|
||||
unsigned NumIntRegs = 0; // Int regs used for parameter passing.
|
||||
unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
|
||||
{
|
||||
CallingConvState CCState(*getTargetMachine().getRegisterInfo());
|
||||
EmptyArgumentsClient Client;
|
||||
|
||||
static const unsigned GPR32ArgRegs[] = {
|
||||
X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
|
||||
};
|
||||
static const unsigned GPR64ArgRegs[] = {
|
||||
X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
|
||||
};
|
||||
static const unsigned XMMArgRegs[] = {
|
||||
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
||||
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
||||
};
|
||||
|
||||
for (unsigned i = 0; i != NumOps; ++i) {
|
||||
SDOperand Arg = Op.getOperand(5+2*i);
|
||||
MVT::ValueType ArgVT = Arg.getValueType();
|
||||
|
||||
switch (ArgVT) {
|
||||
default: assert(0 && "Unknown value type!");
|
||||
case MVT::i8:
|
||||
case MVT::i16:
|
||||
case MVT::i32:
|
||||
case MVT::i64:
|
||||
if (NumIntRegs < 6)
|
||||
++NumIntRegs;
|
||||
else
|
||||
NumBytes += 8;
|
||||
break;
|
||||
case MVT::f32:
|
||||
case MVT::f64:
|
||||
case MVT::v16i8:
|
||||
case MVT::v8i16:
|
||||
case MVT::v4i32:
|
||||
case MVT::v2i64:
|
||||
case MVT::v4f32:
|
||||
case MVT::v2f64:
|
||||
if (NumXMMRegs < 8)
|
||||
NumXMMRegs++;
|
||||
else if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
|
||||
NumBytes += 8;
|
||||
else {
|
||||
// XMM arguments have to be aligned on 16-byte boundary.
|
||||
NumBytes = ((NumBytes + 15) / 16) * 16;
|
||||
NumBytes += 16;
|
||||
}
|
||||
break;
|
||||
for (unsigned i = 0; i != NumOps; ++i) {
|
||||
SDOperand Arg = Op.getOperand(5+2*i);
|
||||
MVT::ValueType ArgVT = Arg.getValueType();
|
||||
unsigned ArgFlags =
|
||||
cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
|
||||
X86_64_CCC_AssignArgument(Client, CCState, ArgVT, ArgFlags, Arg);
|
||||
}
|
||||
|
||||
NumBytes = CCState.getNextStackOffset();
|
||||
}
|
||||
|
||||
|
||||
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
|
||||
|
||||
// Arguments go on the stack in reverse order, as specified by the ABI.
|
||||
unsigned ArgOffset = 0;
|
||||
NumIntRegs = 0;
|
||||
NumXMMRegs = 0;
|
||||
SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
|
||||
SmallVector<SDOperand, 8> MemOpChains;
|
||||
SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
|
||||
|
||||
CallingConvState CCState(*getTargetMachine().getRegisterInfo());
|
||||
LowerCallArgumentsClient Client(DAG, *this, RegsToPass, MemOpChains, Chain);
|
||||
|
||||
for (unsigned i = 0; i != NumOps; ++i) {
|
||||
SDOperand Arg = Op.getOperand(5+2*i);
|
||||
MVT::ValueType ArgVT = Arg.getValueType();
|
||||
unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
|
||||
|
||||
if (MVT::isInteger(ArgVT) && ArgVT < MVT::i32) {
|
||||
// Promote the integer to 32 bits. If the input type is signed use a
|
||||
// sign extend, otherwise use a zero extend.
|
||||
unsigned ExtOpc = (ArgFlags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
|
||||
Arg = DAG.getNode(ExtOpc, MVT::i32, Arg);
|
||||
ArgVT = MVT::i32;
|
||||
}
|
||||
|
||||
switch (ArgVT) {
|
||||
default: assert(0 && "Unexpected ValueType for argument!");
|
||||
case MVT::i8:
|
||||
case MVT::i16:
|
||||
case MVT::i32:
|
||||
case MVT::i64:
|
||||
if (NumIntRegs < 6) {
|
||||
unsigned Reg = 0;
|
||||
switch (ArgVT) {
|
||||
default: assert(0 && "Unknown integer size!");
|
||||
case MVT::i32:
|
||||
Reg = GPR32ArgRegs[NumIntRegs];
|
||||
break;
|
||||
case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break;
|
||||
}
|
||||
RegsToPass.push_back(std::make_pair(Reg, Arg));
|
||||
++NumIntRegs;
|
||||
} else {
|
||||
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
||||
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
|
||||
ArgOffset += 8;
|
||||
}
|
||||
break;
|
||||
case MVT::f32:
|
||||
case MVT::f64:
|
||||
case MVT::v16i8:
|
||||
case MVT::v8i16:
|
||||
case MVT::v4i32:
|
||||
case MVT::v2i64:
|
||||
case MVT::v4f32:
|
||||
case MVT::v2f64:
|
||||
if (NumXMMRegs < 8) {
|
||||
RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
|
||||
NumXMMRegs++;
|
||||
} else {
|
||||
if (ArgVT != MVT::f32 && ArgVT != MVT::f64) {
|
||||
// XMM arguments have to be aligned on 16-byte boundary.
|
||||
ArgOffset = ((ArgOffset + 15) / 16) * 16;
|
||||
}
|
||||
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
||||
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
|
||||
if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
|
||||
ArgOffset += 8;
|
||||
else
|
||||
ArgOffset += 16;
|
||||
}
|
||||
}
|
||||
unsigned ArgFlags =
|
||||
cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
|
||||
X86_64_CCC_AssignArgument(Client, CCState, ArgVT, ArgFlags, Arg);
|
||||
}
|
||||
|
||||
if (!MemOpChains.empty())
|
||||
|
|
@ -1447,6 +1469,14 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
|||
// of SSE registers used. The contents of %al do not need to match exactly
|
||||
// the number of registers, but must be an ubound on the number of SSE
|
||||
// registers used and is in the range 0 - 8 inclusive.
|
||||
|
||||
// Count the number of XMM registers allocated.
|
||||
static const unsigned XMMArgRegs[] = {
|
||||
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
||||
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
||||
};
|
||||
unsigned NumXMMRegs = CCState.getFirstUnallocated(XMMArgRegs, 8);
|
||||
|
||||
Chain = DAG.getCopyToReg(Chain, X86::AL,
|
||||
DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
|
||||
InFlag = Chain.getValue(1);
|
||||
|
|
@ -1523,8 +1553,6 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
|||
// This calling convention always arranges for the callee pop value to be 8n+4
|
||||
// bytes, which is needed for tail recursion elimination and stack alignment
|
||||
// reasons.
|
||||
|
||||
|
||||
SDOperand
|
||||
X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
|
||||
bool isFastCall) {
|
||||
|
|
@ -1670,7 +1698,7 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
|
|||
|
||||
// Return the new list of results.
|
||||
return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
|
||||
&ArgValues[0], ArgValues.size());
|
||||
&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
|
||||
}
|
||||
|
||||
SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
||||
|
|
|
|||
Loading…
Reference in New Issue