forked from OSchip/llvm-project
[X86] Remove remaining system/special schedule itineraries (PR37093)
llvm-svn: 329906
This commit is contained in:
Simon Pilgrim
parent
a5a3c38c3d
commit
294556d40e
|
|
@ -8833,8 +8833,8 @@ multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeSt
|
|||
RegisterClass KRC, X86MemOperand memop> {
|
||||
let Predicates = [HasPFI], hasSideEffects = 1 in
|
||||
def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
|
||||
!strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
|
||||
[], IIC_SSE_PREFETCH>, EVEX, EVEX_K, Sched<[WriteLoad]>;
|
||||
!strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"), []>,
|
||||
EVEX, EVEX_K, Sched<[WriteLoad]>;
|
||||
}
|
||||
|
||||
defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
|
||||
|
|
|
|||
|
|
@ -317,8 +317,7 @@ def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
|
|||
// that would make it more difficult to rematerialize.
|
||||
let isReMaterializable = 1, isAsCheapAsAMove = 1,
|
||||
isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
|
||||
def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", [],
|
||||
IIC_MOV>;
|
||||
def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>;
|
||||
|
||||
// This 64-bit pseudo-move can be used for both a 64-bit constant that is
|
||||
// actually the zero-extension of a 32-bit constant and for labels in the
|
||||
|
|
@ -396,28 +395,28 @@ def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
|
|||
let SchedRW = [WriteMicrocoded] in {
|
||||
let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
|
||||
def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
|
||||
[(X86rep_movs i8)], IIC_REP_MOVS>, REP,
|
||||
[(X86rep_movs i8)]>, REP,
|
||||
Requires<[Not64BitMode]>;
|
||||
def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
|
||||
[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
|
||||
[(X86rep_movs i16)]>, REP, OpSize16,
|
||||
Requires<[Not64BitMode]>;
|
||||
def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
|
||||
[(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
|
||||
[(X86rep_movs i32)]>, REP, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
}
|
||||
|
||||
let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
|
||||
def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
|
||||
[(X86rep_movs i8)], IIC_REP_MOVS>, REP,
|
||||
[(X86rep_movs i8)]>, REP,
|
||||
Requires<[In64BitMode]>;
|
||||
def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
|
||||
[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
|
||||
[(X86rep_movs i16)]>, REP, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
|
||||
[(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
|
||||
[(X86rep_movs i32)]>, REP, OpSize32,
|
||||
Requires<[In64BitMode]>;
|
||||
def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
|
||||
[(X86rep_movs i64)], IIC_REP_MOVS>, REP,
|
||||
[(X86rep_movs i64)]>, REP,
|
||||
Requires<[In64BitMode]>;
|
||||
}
|
||||
|
||||
|
|
@ -425,36 +424,36 @@ def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
|
|||
let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
|
||||
let Uses = [AL,ECX,EDI] in
|
||||
def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
|
||||
[(X86rep_stos i8)], IIC_REP_STOS>, REP,
|
||||
[(X86rep_stos i8)]>, REP,
|
||||
Requires<[Not64BitMode]>;
|
||||
let Uses = [AX,ECX,EDI] in
|
||||
def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
|
||||
[(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
|
||||
[(X86rep_stos i16)]>, REP, OpSize16,
|
||||
Requires<[Not64BitMode]>;
|
||||
let Uses = [EAX,ECX,EDI] in
|
||||
def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
|
||||
[(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
|
||||
[(X86rep_stos i32)]>, REP, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
}
|
||||
|
||||
let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
|
||||
let Uses = [AL,RCX,RDI] in
|
||||
def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
|
||||
[(X86rep_stos i8)], IIC_REP_STOS>, REP,
|
||||
Requires<[In64BitMode]>;
|
||||
[(X86rep_stos i8)]>, REP,
|
||||
Requires<[In64BitMode]>;
|
||||
let Uses = [AX,RCX,RDI] in
|
||||
def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
|
||||
[(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
[(X86rep_stos i16)]>, REP, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
let Uses = [RAX,RCX,RDI] in
|
||||
def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
|
||||
[(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
|
||||
Requires<[In64BitMode]>;
|
||||
[(X86rep_stos i32)]>, REP, OpSize32,
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
let Uses = [RAX,RCX,RDI] in
|
||||
def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
|
||||
[(X86rep_stos i64)], IIC_REP_STOS>, REP,
|
||||
Requires<[In64BitMode]>;
|
||||
[(X86rep_stos i64)]>, REP,
|
||||
Requires<[In64BitMode]>;
|
||||
}
|
||||
} // SchedRW
|
||||
|
||||
|
|
@ -759,43 +758,39 @@ defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "X86lock_dec", "dec">;
|
|||
|
||||
// Atomic compare and swap.
|
||||
multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
|
||||
SDPatternOperator frag, X86MemOperand x86memop,
|
||||
InstrItinClass itin> {
|
||||
SDPatternOperator frag, X86MemOperand x86memop> {
|
||||
let isCodeGenOnly = 1, usesCustomInserter = 1 in {
|
||||
def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
|
||||
!strconcat(mnemonic, "\t$ptr"),
|
||||
[(frag addr:$ptr)], itin>, TB, LOCK;
|
||||
[(frag addr:$ptr)]>, TB, LOCK;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
|
||||
string mnemonic, SDPatternOperator frag,
|
||||
InstrItinClass itin8, InstrItinClass itin> {
|
||||
string mnemonic, SDPatternOperator frag> {
|
||||
let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
let Defs = [AL, EFLAGS], Uses = [AL] in
|
||||
def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
|
||||
!strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
|
||||
[(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
|
||||
let Defs = [AX, EFLAGS], Uses = [AX] in
|
||||
def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
|
||||
!strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
|
||||
[(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK;
|
||||
let Defs = [EAX, EFLAGS], Uses = [EAX] in
|
||||
def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
|
||||
!strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
|
||||
[(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK;
|
||||
let Defs = [RAX, EFLAGS], Uses = [RAX] in
|
||||
def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
|
||||
!strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
|
||||
[(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
|
||||
}
|
||||
}
|
||||
|
||||
let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
|
||||
SchedRW = [WriteALULd, WriteRMW] in {
|
||||
defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
|
||||
X86cas8, i64mem,
|
||||
IIC_CMPX_LOCK_8B>;
|
||||
defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>;
|
||||
}
|
||||
|
||||
// This pseudo must be used when the frame uses RBX as
|
||||
|
|
@ -825,16 +820,14 @@ def LCMPXCHG8B_SAVE_EBX :
|
|||
(ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save),
|
||||
!strconcat("cmpxchg8b", "\t$ptr"),
|
||||
[(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input,
|
||||
GR32:$ebx_save))],
|
||||
IIC_CMPX_LOCK_8B>;
|
||||
GR32:$ebx_save))]>;
|
||||
}
|
||||
|
||||
|
||||
let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
|
||||
Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
|
||||
defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
|
||||
X86cas16, i128mem,
|
||||
IIC_CMPX_LOCK_16B>, REX_W;
|
||||
X86cas16, i128mem>, REX_W;
|
||||
}
|
||||
|
||||
// Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant.
|
||||
|
|
@ -847,52 +840,45 @@ def LCMPXCHG16B_SAVE_RBX :
|
|||
(ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save),
|
||||
!strconcat("cmpxchg16b", "\t$ptr"),
|
||||
[(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input,
|
||||
GR64:$rbx_save))],
|
||||
IIC_CMPX_LOCK_16B>;
|
||||
GR64:$rbx_save))]>;
|
||||
}
|
||||
|
||||
defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
|
||||
X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
|
||||
defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>;
|
||||
|
||||
// Atomic exchange and add
|
||||
multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
|
||||
string frag,
|
||||
InstrItinClass itin8, InstrItinClass itin> {
|
||||
string frag> {
|
||||
let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
|
||||
SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
|
||||
(ins GR8:$val, i8mem:$ptr),
|
||||
!strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set GR8:$dst,
|
||||
(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
|
||||
itin8>;
|
||||
(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>;
|
||||
def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
|
||||
(ins GR16:$val, i16mem:$ptr),
|
||||
!strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR16:$dst,
|
||||
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
|
||||
itin>, OpSize16;
|
||||
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>,
|
||||
OpSize16;
|
||||
def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
|
||||
(ins GR32:$val, i32mem:$ptr),
|
||||
!strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR32:$dst,
|
||||
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
|
||||
itin>, OpSize32;
|
||||
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>,
|
||||
OpSize32;
|
||||
def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$val, i64mem:$ptr),
|
||||
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR64:$dst,
|
||||
(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
|
||||
itin>;
|
||||
(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>;
|
||||
}
|
||||
}
|
||||
|
||||
defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
|
||||
IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
|
||||
TB, LOCK;
|
||||
defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK;
|
||||
|
||||
/* The following multiclass tries to make sure that in code like
|
||||
* x.store (immediate op x.load(acquire), release)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -3488,46 +3488,39 @@ let Predicates = [UseSSE2] in {
|
|||
// Prefetch intrinsic.
|
||||
let Predicates = [HasSSEPrefetch], SchedRW = [WriteLoad] in {
|
||||
def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
|
||||
"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
|
||||
IIC_SSE_PREFETCH>, TB;
|
||||
"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB;
|
||||
def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
|
||||
"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
|
||||
IIC_SSE_PREFETCH>, TB;
|
||||
"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB;
|
||||
def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
|
||||
"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
|
||||
IIC_SSE_PREFETCH>, TB;
|
||||
"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB;
|
||||
def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
|
||||
"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
|
||||
IIC_SSE_PREFETCH>, TB;
|
||||
"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB;
|
||||
}
|
||||
|
||||
// FIXME: How should flush instruction be modeled?
|
||||
let SchedRW = [WriteLoad] in {
|
||||
// Flush cache
|
||||
def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
|
||||
"clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
|
||||
IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
|
||||
"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
|
||||
PS, Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
let SchedRW = [WriteNop] in {
|
||||
// Pause. This "instruction" is encoded as "rep; nop", so even though it
|
||||
// was introduced with SSE2, it's backward compatible.
|
||||
def PAUSE : I<0x90, RawFrm, (outs), (ins),
|
||||
"pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>, OBXS;
|
||||
"pause", [(int_x86_sse2_pause)]>, OBXS;
|
||||
}
|
||||
|
||||
let SchedRW = [WriteFence] in {
|
||||
// Load, store, and memory fence
|
||||
// TODO: As with mfence, we may want to ease the availablity of sfence/lfence
|
||||
// to include any 64-bit target.
|
||||
def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
|
||||
"sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
|
||||
def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
|
||||
PS, Requires<[HasSSE1]>;
|
||||
def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
|
||||
"lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
|
||||
def LFENCE : I<0xAE, MRM_E8, (outs), (ins), "lfence", [(int_x86_sse2_lfence)]>,
|
||||
TB, Requires<[HasSSE2]>;
|
||||
def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
|
||||
"mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
|
||||
def MFENCE : I<0xAE, MRM_F0, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
|
||||
TB, Requires<[HasMFence]>;
|
||||
} // SchedRW
|
||||
|
||||
|
|
@ -3538,18 +3531,18 @@ def : Pat<(X86MFence), (MFENCE)>;
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
|
||||
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
|
||||
IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>, VEX_WIG;
|
||||
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>,
|
||||
VEX, Sched<[WriteLoad]>, VEX_WIG;
|
||||
def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
|
||||
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
|
||||
IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>, VEX_WIG;
|
||||
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>,
|
||||
VEX, Sched<[WriteStore]>, VEX_WIG;
|
||||
|
||||
def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
|
||||
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
|
||||
IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
|
||||
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>,
|
||||
TB, Sched<[WriteLoad]>;
|
||||
def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
|
||||
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
|
||||
IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
|
||||
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>,
|
||||
TB, Sched<[WriteStore]>;
|
||||
|
||||
//===---------------------------------------------------------------------===//
|
||||
// SSE2 - Move Aligned/Unaligned Packed Integer Instructions
|
||||
|
|
@ -5306,13 +5299,12 @@ def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
|
|||
}
|
||||
|
||||
let Uses = [EAX, ECX, EDX] in
|
||||
def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
|
||||
TB, Requires<[HasSSE3]>;
|
||||
def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>,
|
||||
TB, Requires<[HasSSE3]>;
|
||||
|
||||
let Uses = [ECX, EAX] in
|
||||
def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
|
||||
[(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
|
||||
TB, Requires<[HasSSE3]>;
|
||||
[(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
|
||||
} // SchedRW
|
||||
|
||||
def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
|
||||
|
|
|
|||
|
|
@ -378,20 +378,6 @@ def IIC_SSE_PMADD : InstrItinClass;
|
|||
def IIC_SSE_PMULHRSW : InstrItinClass;
|
||||
def IIC_SSE_PALIGNRR : InstrItinClass;
|
||||
def IIC_SSE_PALIGNRM : InstrItinClass;
|
||||
def IIC_SSE_MWAIT : InstrItinClass;
|
||||
def IIC_SSE_MONITOR : InstrItinClass;
|
||||
def IIC_SSE_MWAITX : InstrItinClass;
|
||||
def IIC_SSE_MONITORX : InstrItinClass;
|
||||
def IIC_SSE_CLZERO : InstrItinClass;
|
||||
|
||||
def IIC_SSE_PREFETCH : InstrItinClass;
|
||||
def IIC_SSE_PAUSE : InstrItinClass;
|
||||
def IIC_SSE_LFENCE : InstrItinClass;
|
||||
def IIC_SSE_MFENCE : InstrItinClass;
|
||||
def IIC_SSE_SFENCE : InstrItinClass;
|
||||
def IIC_SSE_LDMXCSR : InstrItinClass;
|
||||
def IIC_SSE_STMXCSR : InstrItinClass;
|
||||
|
||||
def IIC_SSE_CVT_PD_RR : InstrItinClass;
|
||||
def IIC_SSE_CVT_PD_RM : InstrItinClass;
|
||||
def IIC_SSE_CVT_PS_RR : InstrItinClass;
|
||||
|
|
@ -407,80 +393,6 @@ def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
|
|||
|
||||
def IIC_AVX_ZERO : InstrItinClass;
|
||||
|
||||
def IIC_CMPX_LOCK : InstrItinClass;
|
||||
def IIC_CMPX_LOCK_8 : InstrItinClass;
|
||||
def IIC_CMPX_LOCK_8B : InstrItinClass;
|
||||
def IIC_CMPX_LOCK_16B : InstrItinClass;
|
||||
|
||||
def IIC_XADD_LOCK_MEM : InstrItinClass;
|
||||
def IIC_XADD_LOCK_MEM8 : InstrItinClass;
|
||||
|
||||
// System instructions
|
||||
def IIC_RDRAND : InstrItinClass;
|
||||
def IIC_RDSEED : InstrItinClass;
|
||||
def IIC_INS : InstrItinClass;
|
||||
def IIC_LWP : InstrItinClass;
|
||||
def IIC_ENTER : InstrItinClass;
|
||||
def IIC_LEAVE : InstrItinClass;
|
||||
def IIC_POP_MEM : InstrItinClass;
|
||||
def IIC_POP_REG16 : InstrItinClass;
|
||||
def IIC_POP_REG : InstrItinClass;
|
||||
def IIC_POP_F : InstrItinClass;
|
||||
def IIC_POP_FD : InstrItinClass;
|
||||
def IIC_POP_A : InstrItinClass;
|
||||
def IIC_PUSH_IMM : InstrItinClass;
|
||||
def IIC_PUSH_MEM : InstrItinClass;
|
||||
def IIC_PUSH_REG : InstrItinClass;
|
||||
def IIC_PUSH_F : InstrItinClass;
|
||||
def IIC_PUSH_A : InstrItinClass;
|
||||
def IIC_BSWAP : InstrItinClass;
|
||||
def IIC_BIT_SCAN_MEM : InstrItinClass;
|
||||
def IIC_BIT_SCAN_REG : InstrItinClass;
|
||||
def IIC_LZCNT_RR : InstrItinClass;
|
||||
def IIC_LZCNT_RM : InstrItinClass;
|
||||
def IIC_TZCNT_RR : InstrItinClass;
|
||||
def IIC_TZCNT_RM : InstrItinClass;
|
||||
def IIC_MOVS : InstrItinClass;
|
||||
def IIC_STOS : InstrItinClass;
|
||||
def IIC_SCAS : InstrItinClass;
|
||||
def IIC_CMPS : InstrItinClass;
|
||||
def IIC_MOV : InstrItinClass;
|
||||
def IIC_MOV_MEM : InstrItinClass;
|
||||
def IIC_AHF : InstrItinClass;
|
||||
def IIC_BT_MI : InstrItinClass;
|
||||
def IIC_BT_MR : InstrItinClass;
|
||||
def IIC_BT_RI : InstrItinClass;
|
||||
def IIC_BT_RR : InstrItinClass;
|
||||
def IIC_BTX_MI : InstrItinClass;
|
||||
def IIC_BTX_MR : InstrItinClass;
|
||||
def IIC_BTX_RI : InstrItinClass;
|
||||
def IIC_BTX_RR : InstrItinClass;
|
||||
def IIC_XCHG_REG : InstrItinClass;
|
||||
def IIC_XCHG_MEM : InstrItinClass;
|
||||
def IIC_XADD_REG : InstrItinClass;
|
||||
def IIC_XADD_MEM : InstrItinClass;
|
||||
def IIC_CMPXCHG_MEM : InstrItinClass;
|
||||
def IIC_CMPXCHG_REG : InstrItinClass;
|
||||
def IIC_CMPXCHG_MEM8 : InstrItinClass;
|
||||
def IIC_CMPXCHG_REG8 : InstrItinClass;
|
||||
def IIC_CMPXCHG_8B : InstrItinClass;
|
||||
def IIC_CMPXCHG_16B : InstrItinClass;
|
||||
def IIC_LODS : InstrItinClass;
|
||||
def IIC_OUTS : InstrItinClass;
|
||||
def IIC_CLC_CMC_STC : InstrItinClass;
|
||||
def IIC_CLD : InstrItinClass;
|
||||
def IIC_STD : InstrItinClass;
|
||||
def IIC_XLAT : InstrItinClass;
|
||||
def IIC_AAA : InstrItinClass;
|
||||
def IIC_AAD : InstrItinClass;
|
||||
def IIC_AAM : InstrItinClass;
|
||||
def IIC_AAS : InstrItinClass;
|
||||
def IIC_DAA : InstrItinClass;
|
||||
def IIC_DAS : InstrItinClass;
|
||||
def IIC_BOUND : InstrItinClass;
|
||||
def IIC_ARPL_REG : InstrItinClass;
|
||||
def IIC_ARPL_MEM : InstrItinClass;
|
||||
def IIC_MOVBE : InstrItinClass;
|
||||
def IIC_AES : InstrItinClass;
|
||||
def IIC_BLEND_MEM : InstrItinClass;
|
||||
def IIC_BLEND_NOMEM : InstrItinClass;
|
||||
|
|
|
|||
Loading…
Reference in New Issue