diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir index 7ccdcb414c28..ecfb9b618f5e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir @@ -370,65 +370,6 @@ body: | --- -name: and_s1_vcc_undef_vcc_undef_vcc -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc - ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 undef %1:sreg_64, undef %2:sreg_64 - ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]] - ; WAVE32-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc - ; WAVE32: $vcc_hi = IMPLICIT_DEF - ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 undef %1:sreg_32, undef %2:sreg_32 - ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]] - %2:vcc(s1) = G_AND undef %0:vcc(s1), undef %1:vcc(s1) - S_ENDPGM 0, implicit %2 -... - ---- - -name: and_s1_sgpr_undef_sgpr_undef_sgpr -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: and_s1_sgpr_undef_sgpr_undef_sgpr - ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc - ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]] - ; WAVE32-LABEL: name: and_s1_sgpr_undef_sgpr_undef_sgpr - ; WAVE32: $vcc_hi = IMPLICIT_DEF - ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc - ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]] - %2:sgpr(s1) = G_AND undef %0:sgpr(s1), undef %1:sgpr(s1) - S_ENDPGM 0, implicit %2 -... - ---- - -name: and_s1_vgpr_undef_vgpr_undef_vgpr -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: and_s1_vgpr_undef_vgpr_undef_vgpr - ; WAVE64: [[AND:%[0-9]+]]:vgpr(s1) = G_AND undef %1:vgpr, undef %2:vgpr - ; WAVE64: S_ENDPGM 0, implicit [[AND]](s1) - ; WAVE32-LABEL: name: and_s1_vgpr_undef_vgpr_undef_vgpr - ; WAVE32: [[AND:%[0-9]+]]:vgpr(s1) = G_AND undef %1:vgpr, undef %2:vgpr - ; WAVE32: S_ENDPGM 0, implicit [[AND]](s1) - %2:vgpr(s1) = G_AND undef %0:vgpr(s1), undef %1:vgpr(s1) - S_ENDPGM 0, implicit %2 -... - ---- - name: and_s1_vcc_copy_to_vcc legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir index 42ce52d3975e..496d496a42c5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir @@ -62,28 +62,6 @@ body: | --- -name: brcond_scc_undef -legalized: true -regBankSelected: true - -body: | - ; GCN-LABEL: name: brcond_scc_undef - ; GCN: bb.0: - ; GCN: successors: %bb.1(0x80000000) - ; GCN: $scc = COPY %0:sgpr_32 - ; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc - ; GCN: bb.1: - bb.0: - liveins: $sgpr0, $sgpr1 - - G_BRCOND undef %0:sgpr(s32), %bb.1 - - bb.1: - -... - ---- - name: brcond_scc_br legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir index b69dcf20dd3c..9cbb2940655a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir @@ -89,46 +89,6 @@ body: | S_ENDPGM 0, implicit %2 ... ---- -name: test_build_vector_s_v2s32_undef_s_s32_s_s32 -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - liveins: $sgpr0 - - ; GCN-LABEL: name: test_build_vector_s_v2s32_undef_s_s32_s_s32 - ; GCN: liveins: $sgpr0 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1 - ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] - %1:sgpr(s32) = COPY $sgpr0 - %2:sgpr(<2 x s32>) = G_BUILD_VECTOR undef %0:sgpr(s32), %1 - S_ENDPGM 0, implicit %2 -... - ---- -name: test_build_vector_s_v2s32_s_s32_undef_s_s32 -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - liveins: $sgpr0 - - ; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_undef_s_s32 - ; GCN: liveins: $sgpr0 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1 - ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] - %0:sgpr(s32) = COPY $sgpr0 - %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, undef %1:sgpr(s32), - S_ENDPGM 0, implicit %2 -... - --- name: test_build_vector_s_v2s64_s_s64_s_s64 legalized: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir index e600aa0e1805..0194dbd563bd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir @@ -239,24 +239,3 @@ body: | S_ENDPGM 0, implicit %2 ... - ---- - -name: copy_s1_vcc_to_vcc_undef -legalized: true -regBankSelected: true - - -body: | - bb.0: - liveins: $sgpr0_sgpr1 - - ; WAVE64-LABEL: name: copy_s1_vcc_to_vcc_undef - ; WAVE64: S_ENDPGM 0, implicit %1:sreg_64_xexec - ; WAVE32-LABEL: name: copy_s1_vcc_to_vcc_undef - ; WAVE32: $vcc_hi = IMPLICIT_DEF - ; WAVE32: S_ENDPGM 0, implicit %1:sreg_32_xm0_xexec - %1:vcc(s1) = COPY undef %0:vcc(s1) - S_ENDPGM 0, implicit %1 - -... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir index 495f6c8ca380..a4c831e25810 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir @@ -89,46 +89,6 @@ body: | S_ENDPGM 0, implicit %2 ... ---- -name: test_merge_values_s_s64_undef_s_s32_s_s32 -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - liveins: $sgpr0 - - ; GCN-LABEL: name: test_merge_values_s_s64_undef_s_s32_s_s32 - ; GCN: liveins: $sgpr0 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1 - ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] - %1:sgpr(s32) = COPY $sgpr0 - %2:sgpr(s64) = G_MERGE_VALUES undef %0:sgpr(s32), %1 - S_ENDPGM 0, implicit %2 -... - ---- -name: test_merge_values_s_s64_s_s32_undef_s_s32 -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - liveins: $sgpr0 - - ; GCN-LABEL: name: test_merge_values_s_s64_s_s32_undef_s_s32 - ; GCN: liveins: $sgpr0 - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1 - ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] - %0:sgpr(s32) = COPY $sgpr0 - %2:sgpr(s64) = G_MERGE_VALUES %0, undef %1:sgpr(s32), - S_ENDPGM 0, implicit %2 -... - --- name: test_merge_values_s_s96_s_s32_s_s32_s_s32 legalized: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir index 2f10cd320320..40b7b69f83b7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir @@ -370,65 +370,6 @@ body: | --- -name: or_s1_vcc_undef_vcc_undef_vcc -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc - ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64 - ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]] - ; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc - ; WAVE32: $vcc_hi = IMPLICIT_DEF - ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32 - ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]] - %2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1) - S_ENDPGM 0, implicit %2 -... - ---- - -name: or_s1_sgpr_undef_sgpr_undef_sgpr -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr - ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc - ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]] - ; WAVE32-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr - ; WAVE32: $vcc_hi = IMPLICIT_DEF - ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc - ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]] - %2:sgpr(s1) = G_OR undef %0:sgpr(s1), undef %1:sgpr(s1) - S_ENDPGM 0, implicit %2 -... - ---- - -name: or_s1_vgpr_undef_vgpr_undef_vgpr -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr - ; WAVE64: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr - ; WAVE64: S_ENDPGM 0, implicit [[OR]](s1) - ; WAVE32-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr - ; WAVE32: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr - ; WAVE32: S_ENDPGM 0, implicit [[OR]](s1) - %2:vgpr(s1) = G_OR undef %0:vgpr(s1), undef %1:vgpr(s1) - S_ENDPGM 0, implicit %2 -... - ---- - name: or_s1_vcc_copy_to_vcc legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir index 7a27911288ac..1c0644f7bf42 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir @@ -85,23 +85,6 @@ body: | S_ENDPGM 0, implicit %1, implicit %2 ... ---- -name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - - ; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src - ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY undef %2.sub0:sreg_64 - ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY undef %2.sub1:sreg_64 - ; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]] - %1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES undef %0:sgpr(s64) - S_ENDPGM 0, implicit %1, implicit %2 -... - --- name: test_unmerge_values_s_s32_s_s32_s32_s_s96 legalized: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir index c81348aa5d89..1c03557cc495 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir @@ -371,65 +371,6 @@ body: | --- -name: xor_s1_vcc_undef_vcc_undef_vcc -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc - ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 undef %1:sreg_64, undef %2:sreg_64 - ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]] - ; WAVE32-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc - ; WAVE32: $vcc_hi = IMPLICIT_DEF - ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 undef %1:sreg_32, undef %2:sreg_32 - ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]] - %2:vcc(s1) = G_XOR undef %0:vcc(s1), undef %1:vcc(s1) - S_ENDPGM 0, implicit %2 -... - ---- - -name: xor_s1_sgpr_undef_sgpr_undef_sgpr -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: xor_s1_sgpr_undef_sgpr_undef_sgpr - ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc - ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]] - ; WAVE32-LABEL: name: xor_s1_sgpr_undef_sgpr_undef_sgpr - ; WAVE32: $vcc_hi = IMPLICIT_DEF - ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc - ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]] - %2:sgpr(s1) = G_XOR undef %0:sgpr(s1), undef %1:sgpr(s1) - S_ENDPGM 0, implicit %2 -... - ---- - -name: xor_s1_vgpr_undef_vgpr_undef_vgpr -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - ; WAVE64-LABEL: name: xor_s1_vgpr_undef_vgpr_undef_vgpr - ; WAVE64: [[XOR:%[0-9]+]]:vgpr(s1) = G_XOR undef %1:vgpr, undef %2:vgpr - ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s1) - ; WAVE32-LABEL: name: xor_s1_vgpr_undef_vgpr_undef_vgpr - ; WAVE32: [[XOR:%[0-9]+]]:vgpr(s1) = G_XOR undef %1:vgpr, undef %2:vgpr - ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s1) - %2:vgpr(s1) = G_XOR undef %0:vgpr(s1), undef %1:vgpr(s1) - S_ENDPGM 0, implicit %2 -... - ---- - name: xor_s1_vcc_copy_to_vcc legalized: true regBankSelected: true