forked from OSchip/llvm-project
AMDGPU/GlobalISel: Remove some selection tests which should be invalid
These use undef generic virtual register operands, which should be rejected by the verifier.
This commit is contained in:
Matt Arsenault
parent
b6c490349d
commit
291ece0efa
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@ -370,65 +370,6 @@ body: |
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---
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name: and_s1_vcc_undef_vcc_undef_vcc
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc
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; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 undef %1:sreg_64, undef %2:sreg_64
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
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; WAVE32-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 undef %1:sreg_32, undef %2:sreg_32
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
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%2:vcc(s1) = G_AND undef %0:vcc(s1), undef %1:vcc(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: and_s1_sgpr_undef_sgpr_undef_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: and_s1_sgpr_undef_sgpr_undef_sgpr
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; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
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; WAVE32-LABEL: name: and_s1_sgpr_undef_sgpr_undef_sgpr
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
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%2:sgpr(s1) = G_AND undef %0:sgpr(s1), undef %1:sgpr(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: and_s1_vgpr_undef_vgpr_undef_vgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: and_s1_vgpr_undef_vgpr_undef_vgpr
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; WAVE64: [[AND:%[0-9]+]]:vgpr(s1) = G_AND undef %1:vgpr, undef %2:vgpr
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; WAVE64: S_ENDPGM 0, implicit [[AND]](s1)
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; WAVE32-LABEL: name: and_s1_vgpr_undef_vgpr_undef_vgpr
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; WAVE32: [[AND:%[0-9]+]]:vgpr(s1) = G_AND undef %1:vgpr, undef %2:vgpr
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; WAVE32: S_ENDPGM 0, implicit [[AND]](s1)
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%2:vgpr(s1) = G_AND undef %0:vgpr(s1), undef %1:vgpr(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: and_s1_vcc_copy_to_vcc
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legalized: true
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regBankSelected: true
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@ -62,28 +62,6 @@ body: |
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---
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name: brcond_scc_undef
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_scc_undef
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: $scc = COPY %0:sgpr_32
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: bb.1:
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bb.0:
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liveins: $sgpr0, $sgpr1
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G_BRCOND undef %0:sgpr(s32), %bb.1
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bb.1:
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...
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---
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name: brcond_scc_br
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legalized: true
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regBankSelected: true
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@ -89,46 +89,6 @@ body: |
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_s_v2s32_undef_s_s32_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: test_build_vector_s_v2s32_undef_s_s32_s_s32
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%1:sgpr(s32) = COPY $sgpr0
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%2:sgpr(<2 x s32>) = G_BUILD_VECTOR undef %0:sgpr(s32), %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_s_v2s32_s_s32_undef_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_undef_s_s32
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, undef %1:sgpr(s32),
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_s_v2s64_s_s64_s_s64
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legalized: true
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@ -239,24 +239,3 @@ body: |
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S_ENDPGM 0, implicit %2
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...
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---
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name: copy_s1_vcc_to_vcc_undef
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; WAVE64-LABEL: name: copy_s1_vcc_to_vcc_undef
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; WAVE64: S_ENDPGM 0, implicit %1:sreg_64_xexec
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; WAVE32-LABEL: name: copy_s1_vcc_to_vcc_undef
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: S_ENDPGM 0, implicit %1:sreg_32_xm0_xexec
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%1:vcc(s1) = COPY undef %0:vcc(s1)
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S_ENDPGM 0, implicit %1
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...
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@ -89,46 +89,6 @@ body: |
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_merge_values_s_s64_undef_s_s32_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: test_merge_values_s_s64_undef_s_s32_s_s32
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%1:sgpr(s32) = COPY $sgpr0
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%2:sgpr(s64) = G_MERGE_VALUES undef %0:sgpr(s32), %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_merge_values_s_s64_s_s32_undef_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: test_merge_values_s_s64_s_s32_undef_s_s32
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%2:sgpr(s64) = G_MERGE_VALUES %0, undef %1:sgpr(s32),
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_merge_values_s_s96_s_s32_s_s32_s_s32
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legalized: true
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@ -370,65 +370,6 @@ body: |
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---
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name: or_s1_vcc_undef_vcc_undef_vcc
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
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; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64
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; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
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; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32
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; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
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%2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: or_s1_sgpr_undef_sgpr_undef_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
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; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
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; WAVE32-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
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%2:sgpr(s1) = G_OR undef %0:sgpr(s1), undef %1:sgpr(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: or_s1_vgpr_undef_vgpr_undef_vgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
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; WAVE64: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
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; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
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; WAVE32-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
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; WAVE32: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
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; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
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%2:vgpr(s1) = G_OR undef %0:vgpr(s1), undef %1:vgpr(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: or_s1_vcc_copy_to_vcc
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legalized: true
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regBankSelected: true
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@ -85,23 +85,6 @@ body: |
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY undef %2.sub0:sreg_64
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY undef %2.sub1:sreg_64
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; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]
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%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES undef %0:sgpr(s64)
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: test_unmerge_values_s_s32_s_s32_s32_s_s96
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legalized: true
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@ -371,65 +371,6 @@ body: |
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---
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name: xor_s1_vcc_undef_vcc_undef_vcc
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc
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; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 undef %1:sreg_64, undef %2:sreg_64
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; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
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; WAVE32-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 undef %1:sreg_32, undef %2:sreg_32
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; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
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%2:vcc(s1) = G_XOR undef %0:vcc(s1), undef %1:vcc(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: xor_s1_sgpr_undef_sgpr_undef_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: xor_s1_sgpr_undef_sgpr_undef_sgpr
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; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
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; WAVE32-LABEL: name: xor_s1_sgpr_undef_sgpr_undef_sgpr
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
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%2:sgpr(s1) = G_XOR undef %0:sgpr(s1), undef %1:sgpr(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: xor_s1_vgpr_undef_vgpr_undef_vgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; WAVE64-LABEL: name: xor_s1_vgpr_undef_vgpr_undef_vgpr
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; WAVE64: [[XOR:%[0-9]+]]:vgpr(s1) = G_XOR undef %1:vgpr, undef %2:vgpr
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; WAVE64: S_ENDPGM 0, implicit [[XOR]](s1)
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; WAVE32-LABEL: name: xor_s1_vgpr_undef_vgpr_undef_vgpr
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; WAVE32: [[XOR:%[0-9]+]]:vgpr(s1) = G_XOR undef %1:vgpr, undef %2:vgpr
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; WAVE32: S_ENDPGM 0, implicit [[XOR]](s1)
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%2:vgpr(s1) = G_XOR undef %0:vgpr(s1), undef %1:vgpr(s1)
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S_ENDPGM 0, implicit %2
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...
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---
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name: xor_s1_vcc_copy_to_vcc
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legalized: true
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regBankSelected: true
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