forked from OSchip/llvm-project
[ARM GlobalISel] Add test for a MOVTi16 pattern. NFC
Add test for matching an OR with 0xFFFF0000 to a MOVTi16. llvm-svn: 320362
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@ -28,6 +28,8 @@
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define void @test_pkhtb_imm16() #0 { ret void }
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define void @test_pkhtb_imm16() #0 { ret void }
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define void @test_pkhtb_imm1_15() #0 { ret void }
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define void @test_pkhtb_imm1_15() #0 { ret void }
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define void @test_movti16_0xffff() #2 { ret void }
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attributes #0 = { "target-features"="+v6" }
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attributes #0 = { "target-features"="+v6" }
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attributes #1 = { "target-features"="-v6" }
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attributes #1 = { "target-features"="-v6" }
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attributes #2 = { "target-features"="+v6t2" }
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attributes #2 = { "target-features"="+v6t2" }
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@ -832,3 +834,32 @@ body: |
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BX_RET 14, %noreg, implicit %r0
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BX_RET 14, %noreg, implicit %r0
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; CHECK: BX_RET 14, %noreg, implicit %r0
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; CHECK: BX_RET 14, %noreg, implicit %r0
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...
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...
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---
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name: test_movti16_0xffff
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# CHECK-LABEL: name: test_movti16_0xffff
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: %r0
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%0(s32) = COPY %r0
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
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%1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
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%2(s32) = G_OR %0, %1
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; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, %noreg
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%r0 = COPY %2(s32)
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; CHECK: %r0 = COPY [[VREGR]]
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BX_RET 14, %noreg, implicit %r0
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; CHECK: BX_RET 14, %noreg, implicit %r0
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...
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