From 28fc173819af223a5bc28e54d8242d3320ed31bf Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 9 Nov 2020 12:14:09 +0000 Subject: [PATCH] [LoopVectorize] Remove unused check-prefixes --- .../AMDGPU/divergent-runtime-check.ll | 2 +- .../ARM/prefer-tail-loop-folding.ll | 2 +- .../LoopVectorize/X86/interleaving.ll | 72 +++++++------------ 3 files changed, 28 insertions(+), 48 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll index 91a916798c53..be9cf85e47d4 100644 --- a/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll +++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -loop-vectorize -simplifycfg < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -loop-vectorize -simplifycfg < %s | FileCheck -check-prefixes=GCN %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -loop-vectorize -pass-remarks-analysis='loop-vectorize' < %s 2>&1 | FileCheck -check-prefixes=REMARK %s ; GCN-LABEL: @runtime_check_divergent_target( diff --git a/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll b/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll index 9180f7f7c3d5..3a8b17d2f8c6 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll @@ -48,7 +48,7 @@ ; RUN: -tail-predication=enabled -loop-vectorize \ ; RUN: -enable-arm-maskedgatscat=false \ ; RUN: -enable-arm-maskedldst=true -S < %s | \ -; RUN: FileCheck %s -check-prefixes=CHECK,FOLDING-OPT +; RUN: FileCheck %s -check-prefixes=CHECK define void @prefer_folding(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C) #0 { ; CHECK-LABEL: prefer_folding( diff --git a/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll b/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll index f8bf35cfcfaa..bd887c072deb 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll @@ -1,30 +1,30 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine < %s | FileCheck %s --check-prefix=NORMAL -; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=sandybridge < %s | FileCheck %s --check-prefixes=AVX,AVX1 -; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=haswell < %s | FileCheck %s --check-prefixes=AVX,AVX2 -; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=slm < %s | FileCheck %s --check-prefix=SLOW -; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=atom < %s | FileCheck %s --check-prefix=SLOW +; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine < %s | FileCheck %s --check-prefix=SSE +; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=sandybridge < %s | FileCheck %s --check-prefix=AVX +; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=haswell < %s | FileCheck %s --check-prefix=AVX +; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=slm < %s | FileCheck %s --check-prefix=SSE +; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=atom < %s | FileCheck %s --check-prefix=SSE define void @foo(i32* noalias nocapture %a, i32* noalias nocapture readonly %b) { -; NORMAL-LABEL: @foo( -; NORMAL-NEXT: entry: -; NORMAL-NEXT: br label [[FOR_BODY:%.*]] -; NORMAL: for.cond.cleanup: -; NORMAL-NEXT: ret void -; NORMAL: for.body: -; NORMAL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] -; NORMAL-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 1 -; NORMAL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]] -; NORMAL-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -; NORMAL-NEXT: [[TMP2:%.*]] = or i64 [[TMP0]], 1 -; NORMAL-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP2]] -; NORMAL-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -; NORMAL-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], [[TMP1]] -; NORMAL-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] -; NORMAL-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX6]], align 4 -; NORMAL-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -; NORMAL-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 1024 -; NORMAL-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]] +; SSE-LABEL: @foo( +; SSE-NEXT: entry: +; SSE-NEXT: br label [[FOR_BODY:%.*]] +; SSE: for.cond.cleanup: +; SSE-NEXT: ret void +; SSE: for.body: +; SSE-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] +; SSE-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 1 +; SSE-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]] +; SSE-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +; SSE-NEXT: [[TMP2:%.*]] = or i64 [[TMP0]], 1 +; SSE-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP2]] +; SSE-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 +; SSE-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], [[TMP1]] +; SSE-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] +; SSE-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX6]], align 4 +; SSE-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 +; SSE-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 1024 +; SSE-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]] ; ; AVX-LABEL: @foo( ; AVX-NEXT: entry: @@ -45,7 +45,7 @@ define void @foo(i32* noalias nocapture %a, i32* noalias nocapture readonly %b) ; AVX-NEXT: store <4 x i32> [[TMP3]], <4 x i32>* [[TMP5]], align 4 ; AVX-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 ; AVX-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 -; AVX-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0 +; AVX-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]] ; AVX: middle.block: ; AVX-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]] ; AVX: scalar.ph: @@ -53,27 +53,7 @@ define void @foo(i32* noalias nocapture %a, i32* noalias nocapture readonly %b) ; AVX: for.cond.cleanup: ; AVX-NEXT: ret void ; AVX: for.body: -; AVX-NEXT: br i1 undef, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !2 -; -; SLOW-LABEL: @foo( -; SLOW-NEXT: entry: -; SLOW-NEXT: br label [[FOR_BODY:%.*]] -; SLOW: for.cond.cleanup: -; SLOW-NEXT: ret void -; SLOW: for.body: -; SLOW-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] -; SLOW-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 1 -; SLOW-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]] -; SLOW-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -; SLOW-NEXT: [[TMP2:%.*]] = or i64 [[TMP0]], 1 -; SLOW-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP2]] -; SLOW-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -; SLOW-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], [[TMP1]] -; SLOW-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] -; SLOW-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX6]], align 4 -; SLOW-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -; SLOW-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 1024 -; SLOW-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]] +; AVX-NEXT: br i1 undef, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], [[LOOP2:!llvm.loop !.*]] ; entry: br label %for.body