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[X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake 

llvm-svn: 320293
This commit is contained in:
Craig Topper 2017-12-10 09:14:42 +00:00
parent 8ade4640f3
commit 28e55386ac
5 changed files with 5 additions and 5 deletions
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2
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -708,7 +708,7 @@ def: InstRW<[BWWriteResGroup7], (instregex "BLSR32rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "BLSR64rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "BZHI32rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "BZHI64rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)r")>;
def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)(_32)?r")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr64")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr64")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSWrr64")>;

2
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -1252,7 +1252,7 @@ def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)r")>;
def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;

2
llvm/lib/Target/X86/X86SchedSandyBridge.td
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@ -469,7 +469,7 @@ def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)r")>;
def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let Latency = 1;

2
llvm/lib/Target/X86/X86SchedSkylakeClient.td
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@ -821,7 +821,7 @@ def: InstRW<[SKLWriteResGroup8], (instregex "BLSR32rr")>;
def: InstRW<[SKLWriteResGroup8], (instregex "BLSR64rr")>;
def: InstRW<[SKLWriteResGroup8], (instregex "BZHI32rr")>;
def: InstRW<[SKLWriteResGroup8], (instregex "BZHI64rr")>;
def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
let Latency = 1;

2
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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@ -1124,7 +1124,7 @@ def: InstRW<[SKXWriteResGroup8], (instregex "BLSR32rr")>;
def: InstRW<[SKXWriteResGroup8], (instregex "BLSR64rr")>;
def: InstRW<[SKXWriteResGroup8], (instregex "BZHI32rr")>;
def: InstRW<[SKXWriteResGroup8], (instregex "BZHI64rr")>;
def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
let Latency = 1;