forked from OSchip/llvm-project
[MIPS][microMIPS] Add a pattern to match TruncIntFP
A pattern needed to match TruncIntFP was missing. This was causing multiple tests from llvm test suite to fail during compilation for micromips. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58722 llvm-svn: 355825
This commit is contained in:
Petar Jovanovic
parent
7f5237bccc
commit
28e13eb098
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@ -1039,7 +1039,7 @@ class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
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class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
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FGR32Opnd, II_TRUNC>;
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class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
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AFGR64Opnd, II_TRUNC>;
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FGR64Opnd, II_TRUNC>;
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class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
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II_SQRT_S, fsqrt>;
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class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
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@ -1749,6 +1749,8 @@ def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
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def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
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def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
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(TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
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def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
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(TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;
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def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
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(ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
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@ -424,6 +424,11 @@ def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
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def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
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(TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
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FGR_32;
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def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
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(CVT_W_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
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FGR_64;
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def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
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(TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6;
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// Selects
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defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
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@ -0,0 +1,418 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M32
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M32
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M32R2-FP64
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M32R2-SF
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M32R3R5
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M32R3R5
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M32R6
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; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M64
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; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M64
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; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M64
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; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=M64R6
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=MMR2-FP32
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=MMR2-FP64
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=MMR2-SF
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=MMR6
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; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\
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; RUN: FileCheck %s -check-prefixes=MMR6-SF
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; Test that fptosi can be matched for MIPS targets for various FPU
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; configurations
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define i32 @test1(float %t) {
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; M32-LABEL: test1:
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; M32: # %bb.0: # %entry
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; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
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; M32-NEXT: # <MCOperand Reg:147>
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; M32-NEXT: # <MCOperand Reg:159>>
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; M32-NEXT: jr $ra # <MCInst #1628 JR
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; M32-NEXT: # <MCOperand Reg:19>>
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; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
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; M32-NEXT: # <MCOperand Reg:321>
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; M32-NEXT: # <MCOperand Reg:147>>
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;
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; M32R2-FP64-LABEL: test1:
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; M32R2-FP64: # %bb.0: # %entry
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; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
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; M32R2-FP64-NEXT: # <MCOperand Reg:147>
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; M32R2-FP64-NEXT: # <MCOperand Reg:159>>
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; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR
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; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
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; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
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; M32R2-FP64-NEXT: # <MCOperand Reg:321>
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; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
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;
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; M32R2-SF-LABEL: test1:
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; M32R2-SF: # %bb.0: # %entry
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; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
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; M32R2-SF-NEXT: # <MCOperand Reg:20>
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; M32R2-SF-NEXT: # <MCOperand Reg:20>
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; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
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; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
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; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; M32R2-SF-NEXT: # <MCInst #2519 SW
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; M32R2-SF-NEXT: # <MCOperand Reg:19>
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; M32R2-SF-NEXT: # <MCOperand Reg:20>
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; M32R2-SF-NEXT: # <MCOperand Imm:20>>
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; M32R2-SF-NEXT: .cfi_offset 31, -4
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; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #1606 JAL
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; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
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; M32R2-SF-NEXT: nop # <MCInst #2370 SLL
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; M32R2-SF-NEXT: # <MCOperand Reg:21>
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; M32R2-SF-NEXT: # <MCOperand Reg:21>
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; M32R2-SF-NEXT: # <MCOperand Imm:0>>
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; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; M32R2-SF-NEXT: # <MCInst #1722 LW
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; M32R2-SF-NEXT: # <MCOperand Reg:19>
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; M32R2-SF-NEXT: # <MCOperand Reg:20>
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; M32R2-SF-NEXT: # <MCOperand Imm:20>>
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; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR
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; M32R2-SF-NEXT: # <MCOperand Reg:19>>
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; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
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; M32R2-SF-NEXT: # <MCOperand Reg:20>
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; M32R2-SF-NEXT: # <MCOperand Reg:20>
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; M32R2-SF-NEXT: # <MCOperand Imm:24>>
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;
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; M32R3R5-LABEL: test1:
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; M32R3R5: # %bb.0: # %entry
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; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
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; M32R3R5-NEXT: # <MCOperand Reg:147>
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; M32R3R5-NEXT: # <MCOperand Reg:159>>
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; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR
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; M32R3R5-NEXT: # <MCOperand Reg:19>>
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; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
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; M32R3R5-NEXT: # <MCOperand Reg:321>
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; M32R3R5-NEXT: # <MCOperand Reg:147>>
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;
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; M32R6-LABEL: test1:
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; M32R6: # %bb.0: # %entry
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; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
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; M32R6-NEXT: # <MCOperand Reg:147>
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; M32R6-NEXT: # <MCOperand Reg:159>>
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; M32R6-NEXT: jr $ra # <MCInst #1607 JALR
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; M32R6-NEXT: # <MCOperand Reg:21>
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; M32R6-NEXT: # <MCOperand Reg:19>>
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; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
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; M32R6-NEXT: # <MCOperand Reg:321>
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; M32R6-NEXT: # <MCOperand Reg:147>>
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;
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; M64-LABEL: test1:
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; M64: # %bb.0: # %entry
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; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
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; M64-NEXT: # <MCOperand Reg:147>
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; M64-NEXT: # <MCOperand Reg:159>>
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; M64-NEXT: jr $ra # <MCInst #1628 JR
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; M64-NEXT: # <MCOperand Reg:301>>
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; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
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; M64-NEXT: # <MCOperand Reg:321>
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; M64-NEXT: # <MCOperand Reg:147>>
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;
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; M64R6-LABEL: test1:
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; M64R6: # %bb.0: # %entry
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; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
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; M64R6-NEXT: # <MCOperand Reg:147>
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; M64R6-NEXT: # <MCOperand Reg:159>>
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; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64
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; M64R6-NEXT: # <MCOperand Reg:355>
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; M64R6-NEXT: # <MCOperand Reg:301>>
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; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
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; M64R6-NEXT: # <MCOperand Reg:321>
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; M64R6-NEXT: # <MCOperand Reg:147>>
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;
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; MMR2-FP32-LABEL: test1:
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; MMR2-FP32: # %bb.0: # %entry
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; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:147>
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; MMR2-FP32-NEXT: # <MCOperand Reg:159>>
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; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
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; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:321>
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; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
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;
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; MMR2-FP64-LABEL: test1:
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; MMR2-FP64: # %bb.0: # %entry
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; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:147>
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; MMR2-FP64-NEXT: # <MCOperand Reg:159>>
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; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
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; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:321>
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; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
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;
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; MMR2-SF-LABEL: test1:
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; MMR2-SF: # %bb.0: # %entry
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; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM
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; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
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; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
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; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM
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; MMR2-SF-NEXT: # <MCOperand Reg:19>
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; MMR2-SF-NEXT: # <MCOperand Reg:20>
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; MMR2-SF-NEXT: # <MCOperand Imm:20>>
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; MMR2-SF-NEXT: .cfi_offset 31, -4
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; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #1621 JAL_MM
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; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
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; MMR2-SF-NEXT: nop # <MCInst #2370 SLL
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; MMR2-SF-NEXT: # <MCOperand Reg:21>
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; MMR2-SF-NEXT: # <MCOperand Reg:21>
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; MMR2-SF-NEXT: # <MCOperand Imm:0>>
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; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM
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; MMR2-SF-NEXT: # <MCOperand Reg:19>
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; MMR2-SF-NEXT: # <MCOperand Reg:20>
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; MMR2-SF-NEXT: # <MCOperand Imm:20>>
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; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM
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; MMR2-SF-NEXT: # <MCOperand Imm:24>>
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; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
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; MMR2-SF-NEXT: # <MCOperand Reg:19>>
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;
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; MMR6-LABEL: test1:
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; MMR6: # %bb.0: # %entry
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; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MMR6
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; MMR6-NEXT: # <MCOperand Reg:147>
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; MMR6-NEXT: # <MCOperand Reg:159>>
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; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
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; MMR6-NEXT: # <MCOperand Reg:321>
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; MMR6-NEXT: # <MCOperand Reg:147>>
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; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
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; MMR6-NEXT: # <MCOperand Reg:19>>
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;
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; MMR6-SF-LABEL: test1:
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; MMR6-SF: # %bb.0: # %entry
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; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
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; MMR6-SF-NEXT: # <MCOperand Reg:20>
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; MMR6-SF-NEXT: # <MCOperand Reg:20>
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; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
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; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
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; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MMR6-SF-NEXT: # <MCInst #2519 SW
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; MMR6-SF-NEXT: # <MCOperand Reg:19>
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; MMR6-SF-NEXT: # <MCOperand Reg:20>
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; MMR6-SF-NEXT: # <MCOperand Imm:20>>
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; MMR6-SF-NEXT: .cfi_offset 31, -4
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; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #1610 JALRC16_MMR6
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; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
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; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MMR6-SF-NEXT: # <MCInst #1722 LW
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; MMR6-SF-NEXT: # <MCOperand Reg:19>
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; MMR6-SF-NEXT: # <MCOperand Reg:20>
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; MMR6-SF-NEXT: # <MCOperand Imm:20>>
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; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
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; MMR6-SF-NEXT: # <MCOperand Reg:20>
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; MMR6-SF-NEXT: # <MCOperand Reg:20>
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; MMR6-SF-NEXT: # <MCOperand Imm:24>>
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; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
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; MMR6-SF-NEXT: # <MCOperand Reg:19>>
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entry:
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%conv = fptosi float %t to i32
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ret i32 %conv
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}
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define i32 @test2(double %t) {
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; M32-LABEL: test2:
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; M32: # %bb.0: # %entry
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; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32
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; M32-NEXT: # <MCOperand Reg:147>
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; M32-NEXT: # <MCOperand Reg:133>>
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; M32-NEXT: jr $ra # <MCInst #1628 JR
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; M32-NEXT: # <MCOperand Reg:19>>
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; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
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; M32-NEXT: # <MCOperand Reg:321>
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; M32-NEXT: # <MCOperand Reg:147>>
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;
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; M32R2-FP64-LABEL: test2:
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; M32R2-FP64: # %bb.0: # %entry
|
||||
; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:147>
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:373>>
|
||||
; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
|
||||
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:321>
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
|
||||
;
|
||||
; M32R2-SF-LABEL: test2:
|
||||
; M32R2-SF: # %bb.0: # %entry
|
||||
; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
|
||||
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
|
||||
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; M32R2-SF-NEXT: # <MCInst #2519 SW
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:19>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; M32R2-SF-NEXT: .cfi_offset 31, -4
|
||||
; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #1606 JAL
|
||||
; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
|
||||
; M32R2-SF-NEXT: nop # <MCInst #2370 SLL
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:21>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:21>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:0>>
|
||||
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; M32R2-SF-NEXT: # <MCInst #1722 LW
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:19>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:19>>
|
||||
; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:24>>
|
||||
;
|
||||
; M32R3R5-LABEL: test2:
|
||||
; M32R3R5: # %bb.0: # %entry
|
||||
; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:147>
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:133>>
|
||||
; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:19>>
|
||||
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:321>
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:147>>
|
||||
;
|
||||
; M32R6-LABEL: test2:
|
||||
; M32R6: # %bb.0: # %entry
|
||||
; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
|
||||
; M32R6-NEXT: # <MCOperand Reg:147>
|
||||
; M32R6-NEXT: # <MCOperand Reg:373>>
|
||||
; M32R6-NEXT: jr $ra # <MCInst #1607 JALR
|
||||
; M32R6-NEXT: # <MCOperand Reg:21>
|
||||
; M32R6-NEXT: # <MCOperand Reg:19>>
|
||||
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
|
||||
; M32R6-NEXT: # <MCOperand Reg:321>
|
||||
; M32R6-NEXT: # <MCOperand Reg:147>>
|
||||
;
|
||||
; M64-LABEL: test2:
|
||||
; M64: # %bb.0: # %entry
|
||||
; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
|
||||
; M64-NEXT: # <MCOperand Reg:147>
|
||||
; M64-NEXT: # <MCOperand Reg:373>>
|
||||
; M64-NEXT: jr $ra # <MCInst #1628 JR
|
||||
; M64-NEXT: # <MCOperand Reg:301>>
|
||||
; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
|
||||
; M64-NEXT: # <MCOperand Reg:321>
|
||||
; M64-NEXT: # <MCOperand Reg:147>>
|
||||
;
|
||||
; M64R6-LABEL: test2:
|
||||
; M64R6: # %bb.0: # %entry
|
||||
; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
|
||||
; M64R6-NEXT: # <MCOperand Reg:147>
|
||||
; M64R6-NEXT: # <MCOperand Reg:373>>
|
||||
; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64
|
||||
; M64R6-NEXT: # <MCOperand Reg:355>
|
||||
; M64R6-NEXT: # <MCOperand Reg:301>>
|
||||
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
|
||||
; M64R6-NEXT: # <MCOperand Reg:321>
|
||||
; M64R6-NEXT: # <MCOperand Reg:147>>
|
||||
;
|
||||
; MMR2-FP32-LABEL: test2:
|
||||
; MMR2-FP32: # %bb.0: # %entry
|
||||
; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:147>
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:133>>
|
||||
; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
|
||||
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:321>
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
|
||||
;
|
||||
; MMR2-FP64-LABEL: test2:
|
||||
; MMR2-FP64: # %bb.0: # %entry
|
||||
; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #1097 CVT_W_D64_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:147>
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:373>>
|
||||
; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
|
||||
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:321>
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
|
||||
;
|
||||
; MMR2-SF-LABEL: test2:
|
||||
; MMR2-SF: # %bb.0: # %entry
|
||||
; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
|
||||
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
|
||||
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:19>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR2-SF-NEXT: .cfi_offset 31, -4
|
||||
; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #1621 JAL_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
|
||||
; MMR2-SF-NEXT: nop # <MCInst #2370 SLL
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:21>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:21>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:0>>
|
||||
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:19>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:24>>
|
||||
; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:19>>
|
||||
;
|
||||
; MMR6-LABEL: test2:
|
||||
; MMR6: # %bb.0: # %entry
|
||||
; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D_MMR6
|
||||
; MMR6-NEXT: # <MCOperand Reg:147>
|
||||
; MMR6-NEXT: # <MCOperand Reg:373>>
|
||||
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:321>
|
||||
; MMR6-NEXT: # <MCOperand Reg:147>>
|
||||
; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:19>>
|
||||
;
|
||||
; MMR6-SF-LABEL: test2:
|
||||
; MMR6-SF: # %bb.0: # %entry
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
|
||||
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
|
||||
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MMR6-SF-NEXT: # <MCInst #2519 SW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:19>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR6-SF-NEXT: .cfi_offset 31, -4
|
||||
; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #1610 JALRC16_MMR6
|
||||
; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
|
||||
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MMR6-SF-NEXT: # <MCInst #1722 LW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:19>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:20>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:24>>
|
||||
; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:19>>
|
||||
entry:
|
||||
%conv = fptosi double %t to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
Loading…
Reference in New Issue