forked from OSchip/llvm-project
Drop interference reassignment in favor of eviction.
The reassignment phase was able to move interference with a higher spill weight, but it didn't happen very often and it was fairly expensive. The existing interference eviction picks up the slack. llvm-svn: 128397
This commit is contained in:
Jakob Stoklund Olesen
parent
86d17d3f76
commit
28d79cdeab
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@ -49,7 +49,6 @@ using namespace llvm;
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STATISTIC(NumGlobalSplits, "Number of split global live ranges");
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STATISTIC(NumLocalSplits, "Number of split local live ranges");
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STATISTIC(NumReassigned, "Number of interferences reassigned");
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STATISTIC(NumEvicted, "Number of interferences evicted");
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static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
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@ -164,10 +163,6 @@ private:
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bool LRE_CanEraseVirtReg(unsigned);
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void LRE_WillShrinkVirtReg(unsigned);
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bool checkUncachedInterference(LiveInterval&, unsigned);
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LiveInterval *getSingleInterference(LiveInterval&, unsigned);
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bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
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void mapGlobalInterference(unsigned, SmallVectorImpl<IndexPair>&);
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float calcSplitConstraints(const SmallVectorImpl<IndexPair>&);
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@ -180,8 +175,6 @@ private:
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unsigned nextSplitPoint(unsigned);
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bool canEvictInterference(LiveInterval&, unsigned, float&);
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unsigned tryReassign(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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unsigned tryEvict(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
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@ -288,17 +281,20 @@ void RAGreedy::enqueue(LiveInterval *LI) {
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unsigned Prio;
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LRStage.grow(Reg);
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if (LRStage[Reg] == RS_Original)
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// 1st generation ranges are handled first, long -> short.
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if (LRStage[Reg] == RS_Second)
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// Unsplit ranges that couldn't be allocated immediately are deferred until
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// everything else has been allocated. Long ranges are allocated last so
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// they are split against realistic interference.
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Prio = (1u << 31) - Size;
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else {
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// Everything else is allocated in long->short order. Long ranges that don't
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// fit should be spilled ASAP so they don't create interference.
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Prio = (1u << 31) + Size;
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else
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// Repeat offenders are handled second, short -> long
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Prio = (1u << 30) - Size;
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// Boost ranges that have a physical register hint.
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const unsigned Hint = VRM->getRegAllocPref(Reg);
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if (TargetRegisterInfo::isPhysicalRegister(Hint))
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Prio |= (1u << 30);
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// Boost ranges that have a physical register hint.
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if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
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Prio |= (1u << 30);
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}
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Queue.push(std::make_pair(Prio, Reg));
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}
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@ -311,100 +307,6 @@ LiveInterval *RAGreedy::dequeue() {
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return LI;
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}
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//===----------------------------------------------------------------------===//
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// Register Reassignment
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//===----------------------------------------------------------------------===//
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// Check interference without using the cache.
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bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
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unsigned PhysReg) {
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for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
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LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
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if (subQ.checkInterference())
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return true;
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}
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return false;
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}
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/// getSingleInterference - Return the single interfering virtual register
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/// assigned to PhysReg. Return 0 if more than one virtual register is
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/// interfering.
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LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
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unsigned PhysReg) {
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// Check physreg and aliases.
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LiveInterval *Interference = 0;
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for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
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LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
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if (Q.checkInterference()) {
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if (Interference)
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return 0;
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if (Q.collectInterferingVRegs(2) > 1)
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return 0;
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Interference = Q.interferingVRegs().front();
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}
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}
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return Interference;
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}
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// Attempt to reassign this virtual register to a different physical register.
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//
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// FIXME: we are not yet caching these "second-level" interferences discovered
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// in the sub-queries. These interferences can change with each call to
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// selectOrSplit. However, we could implement a "may-interfere" cache that
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// could be conservatively dirtied when we reassign or split.
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//
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// FIXME: This may result in a lot of alias queries. We could summarize alias
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// live intervals in their parent register's live union, but it's messy.
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bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
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unsigned WantedPhysReg) {
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assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
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"Can only reassign virtual registers");
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assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
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"inconsistent phys reg assigment");
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AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
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while (unsigned PhysReg = Order.next()) {
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// Don't reassign to a WantedPhysReg alias.
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if (TRI->regsOverlap(PhysReg, WantedPhysReg))
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continue;
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if (checkUncachedInterference(InterferingVReg, PhysReg))
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continue;
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// Reassign the interfering virtual reg to this physical reg.
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unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
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DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
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TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
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unassign(InterferingVReg, OldAssign);
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assign(InterferingVReg, PhysReg);
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++NumReassigned;
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return true;
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}
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return false;
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}
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/// tryReassign - Try to reassign a single interference to a different physreg.
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/// @param VirtReg Currently unassigned virtual register.
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/// @param Order Physregs to try.
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/// @return Physreg to assign VirtReg, or 0.
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unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order,
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SmallVectorImpl<LiveInterval*> &NewVRegs){
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NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
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Order.rewind();
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while (unsigned PhysReg = Order.next()) {
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LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
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if (!InterferingVReg)
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
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continue;
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if (reassignVReg(*InterferingVReg, PhysReg))
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return PhysReg;
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}
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return 0;
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}
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//===----------------------------------------------------------------------===//
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// Interference eviction
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//===----------------------------------------------------------------------===//
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@ -851,22 +753,8 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
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SE->finish();
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++NumGlobalSplits;
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if (VerifyEnabled) {
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if (VerifyEnabled)
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MF->verify(this, "After splitting live range around region");
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#ifndef NDEBUG
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// Make sure that at least one of the new intervals can allocate to PhysReg.
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// That was the whole point of splitting the live range.
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bool found = false;
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for (LiveRangeEdit::iterator I = LREdit.begin(), E = LREdit.end(); I != E;
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++I)
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if (!checkUncachedInterference(**I, PhysReg)) {
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found = true;
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break;
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}
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assert(found && "No allocatable intervals after pointless splitting");
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#endif
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}
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}
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unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
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@ -1242,10 +1130,6 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
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unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &NewVRegs) {
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LiveRangeStage Stage = getStage(VirtReg);
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if (Stage == RS_Original)
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LRStage[VirtReg.reg] = RS_Second;
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// First try assigning a free register.
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AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
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while (unsigned PhysReg = Order.next()) {
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@ -1253,9 +1137,6 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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return PhysReg;
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}
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if (unsigned PhysReg = tryReassign(VirtReg, Order, NewVRegs))
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return PhysReg;
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if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
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return PhysReg;
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@ -1264,7 +1145,9 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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// The first time we see a live range, don't try to split or spill.
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// Wait until the second time, when all smaller ranges have been allocated.
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// This gives a better picture of the interference to split around.
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LiveRangeStage Stage = getStage(VirtReg);
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if (Stage == RS_Original) {
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LRStage[VirtReg.reg] = RS_Second;
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DEBUG(dbgs() << "wait for second round\n");
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NewVRegs.push_back(&VirtReg);
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return 0;
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