forked from OSchip/llvm-project
[LLD][ELF][ARM] Implement ARM pc-relative relocations for ADR and LDR
The R_ARM_ALU_PC_G0 and R_ARM_LDR_PC_G0 relocations are used by the ADR and LDR pseudo instructions, and are the basis of the group relocations that can load an arbitrary constant via a series of add, sub and ldr instructions. The relocations need to be obtained via the .reloc directive. R_ARM_ALU_PC_G0 is much more complicated as the add/sub instruction uses a modified immediate encoding of an 8-bit immediate rotated right by an even 4-bit field. This means that the range of representable immediates is sparse. We extract the encoding and decoding functions for the modified immediate from llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h as this header file is not accessible from LLD. Duplication of code isn't ideal, but as these are well-defined mathematical functions they are unlikely to change. Differential Revision: https://reviews.llvm.org/D75349
This commit is contained in:
Peter Smith
parent
66c18c729d
commit
28b172e341
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@ -132,6 +132,8 @@ RelExpr ARM::getRelExpr(RelType type, const Symbol &s,
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case R_ARM_THM_MOVW_PREL_NC:
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case R_ARM_THM_MOVT_PREL:
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return R_PC;
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case R_ARM_ALU_PC_G0:
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case R_ARM_LDR_PC_G0:
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case R_ARM_THM_ALU_PREL_11_0:
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case R_ARM_THM_PC8:
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case R_ARM_THM_PC12:
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@ -410,6 +412,58 @@ static void stateChangeWarning(uint8_t *loc, RelType relt, const Symbol &s) {
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}
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}
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// Utility functions taken from ARMAddressingModes.h, only changes are LLD
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// coding style.
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// Rotate a 32-bit unsigned value right by a specified amt of bits.
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static uint32_t rotr32(uint32_t val, uint32_t amt) {
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assert(amt < 32 && "Invalid rotate amount");
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return (val >> amt) | (val << ((32 - amt) & 31));
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}
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// Rotate a 32-bit unsigned value left by a specified amt of bits.
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static uint32_t rotl32(uint32_t val, uint32_t amt) {
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assert(amt < 32 && "Invalid rotate amount");
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return (val << amt) | (val >> ((32 - amt) & 31));
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}
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// Try to encode a 32-bit unsigned immediate imm with an immediate shifter
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// operand, this form is an 8-bit immediate rotated right by an even number of
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// bits. We compute the rotate amount to use. If this immediate value cannot be
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// handled with a single shifter-op, determine a good rotate amount that will
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// take a maximal chunk of bits out of the immediate.
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static uint32_t getSOImmValRotate(uint32_t imm) {
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// 8-bit (or less) immediates are trivially shifter_operands with a rotate
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// of zero.
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if ((imm & ~255U) == 0)
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return 0;
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// Use CTZ to compute the rotate amount.
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unsigned tz = llvm::countTrailingZeros(imm);
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// Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
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// not 9.
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unsigned rotAmt = tz & ~1;
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// If we can handle this spread, return it.
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if ((rotr32(imm, rotAmt) & ~255U) == 0)
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return (32 - rotAmt) & 31; // HW rotates right, not left.
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// For values like 0xF000000F, we should ignore the low 6 bits, then
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// retry the hunt.
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if (imm & 63U) {
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unsigned tz2 = countTrailingZeros(imm & ~63U);
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unsigned rotAmt2 = tz2 & ~1;
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if ((rotr32(imm, rotAmt2) & ~255U) == 0)
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return (32 - rotAmt2) & 31; // HW rotates right, not left.
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}
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// Otherwise, we have no way to cover this span of bits with a single
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// shifter_op immediate. Return a chunk of bits that will be useful to
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// handle.
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return (32 - rotAmt) & 31; // HW rotates right, not left.
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}
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void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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switch (rel.type) {
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case R_ARM_ABS32:
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@ -574,6 +628,45 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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((val << 4) & 0x7000) | // imm3
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(val & 0x00ff)); // imm8
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break;
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case R_ARM_ALU_PC_G0: {
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// ADR (literal) add = bit23, sub = bit22
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// literal is a 12-bit modified immediate, made up of a 4-bit even rotate
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// right and an 8-bit immediate. The code-sequence here is derived from
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// ARMAddressingModes.h in llvm/Target/ARM/MCTargetDesc. In our case we
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// want to give an error if we cannot encode the constant.
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uint32_t opcode = 0x00800000;
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if (val >> 63) {
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opcode = 0x00400000;
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val = ~val + 1;
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}
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if ((val & ~255U) != 0) {
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uint32_t rotAmt = getSOImmValRotate(val);
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// Error if we cannot encode this with a single shift
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if (rotr32(~255U, rotAmt) & val)
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error(getErrorLocation(loc) + "unencodeable immediate " +
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Twine(val).str() + " for relocation " + toString(rel.type));
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val = rotl32(val, rotAmt) | ((rotAmt >> 1) << 8);
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}
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write32le(loc, (read32le(loc) & 0xff0ff000) | opcode | val);
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break;
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}
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case R_ARM_LDR_PC_G0: {
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// R_ARM_LDR_PC_G0 is S + A - P, we have ((S + A) | T) - P, if S is a
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// function then addr is 0 (modulo 2) and Pa is 0 (modulo 4) so we can clear
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// bottom bit to recover S + A - P.
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if (rel.sym->isFunc())
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val &= ~0x1;
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// LDR (literal) u = bit23
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int64_t imm = val;
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uint32_t u = 0x00800000;
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if (imm < 0) {
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imm = -imm;
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u = 0;
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}
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checkUInt(loc, imm, 12, rel);
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write32le(loc, (read32le(loc) & 0xff7ff000) | u | imm);
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break;
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}
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case R_ARM_THM_ALU_PREL_11_0: {
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// ADR encoding T2 (sub), T3 (add) i:imm3:imm8
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int64_t imm = val;
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@ -708,6 +801,22 @@ int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
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((lo & 0x7000) >> 4) | // imm3
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(lo & 0x00ff)); // imm8
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}
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case R_ARM_ALU_PC_G0: {
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// 12-bit immediate is a modified immediate made up of a 4-bit even
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// right rotation and 8-bit constant. After the rotation the value
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// is zero-extended. When bit 23 is set the instruction is an add, when
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// bit 22 is set it is a sub.
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uint32_t instr = read32le(buf);
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uint32_t val = rotr32(instr & 0xff, ((instr & 0xf00) >> 8) * 2);
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return (instr & 0x00400000) ? -val : val;
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}
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case R_ARM_LDR_PC_G0: {
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// ADR (literal) add = bit23, sub = bit22
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// LDR (literal) u = bit23 unsigned imm12
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bool u = read32le(buf) & 0x00800000;
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uint32_t imm12 = read32le(buf) & 0xfff;
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return u ? imm12 : -imm12;
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}
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case R_ARM_THM_ALU_PREL_11_0: {
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// Thumb2 ADR, which is an alias for a sub or add instruction with an
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// unsigned immediate.
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@ -0,0 +1,30 @@
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// REQUIRES: arm
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// RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s
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.section .os0, "ax", %progbits
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.balign 1024
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.thumb_func
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low:
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bx lr
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/// Check that we error when the immediate for the add or sub is not encodeable
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.section .os1, "ax", %progbits
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.arm
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.balign 1024
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.global _start
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.type _start, %function
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_start:
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// CHECK: {{.*}}.s.tmp.o:(.os1+0x0): unencodeable immediate 1031 for relocation R_ARM_ALU_PC_G0
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/// adr r0, low
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.inst 0xe24f0008
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.reloc 0, R_ARM_ALU_PC_G0, low
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// CHECK: {{.*}}.s.tmp.o:(.os1+0x4): unencodeable immediate 1013 for relocation R_ARM_ALU_PC_G0
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/// adr r1, unaligned
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.inst 0xe24f1008
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.reloc 4, R_ARM_ALU_PC_G0, unaligned
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.section .os2, "ax", %progbits
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.balign 1024
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.thumb_func
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unaligned:
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bx lr
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@ -0,0 +1,42 @@
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// REQUIRES: arm
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// RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: echo "SECTIONS { \
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// RUN: .text.0 0x10000000 : { *(.text.0) } \
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// RUN: .text.1 0x80000000 : { *(.text.1) } \
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// RUN: .text.2 0xf0000010 : { *(.text.2) } \
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// RUN: } " > %t.script
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// RUN: ld.lld --script %t.script %t.o -o %t
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// RUN: llvm-objdump -d --no-show-raw-insn --triple=armv7a-none-eabi %t | FileCheck %s
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/// Test the long range encoding of R_ARM_ALU_PC_G0. We can encode an 8-bit
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/// immediate rotated right by an even 4-bit field.
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.section .text.0, "ax", %progbits
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dat1:
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.word 0
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.section .text.1, "ax", %progbits
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.global _start
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.type _start, %function
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_start:
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/// adr.w r0, dat1
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.inst 0xe24f0008
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.reloc 0, R_ARM_ALU_PC_G0, dat1
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/// adr.w r1, dat2
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.inst 0xe24f1008
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.reloc 4, R_ARM_ALU_PC_G0, dat2
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.section .text.2, "ax", %progbits
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dat2:
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.word 0
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// CHECK: 10000000 <dat1>:
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// CHECK-NEXT: 10000000: andeq r0, r0, r0
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// CHECK: 80000000 <_start>:
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/// 0x80000000 + 0x8 - 0x70000008 = 0x10000000
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// CHECK-NEXT: 80000000: sub r0, pc, #1879048200
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/// 0x80000004 + 0x8 + 0x70000004 = 0xf0000010
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// CHECK-NEXT: 80000004: add r1, pc, #1879048196
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// CHECK: f0000010 <dat2>:
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// CHECK-NEXT: f0000010: andeq r0, r0, r0
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@ -0,0 +1,111 @@
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// REQUIRES: arm
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// RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: ld.lld %t.o -o %t
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// RUN: llvm-objdump -d --no-show-raw-insn --triple=armv7a-none-eabi %t | FileCheck %s
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/// Test the short range cases of R_ARM_ALU_PC_G0. The range of the instruction
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/// depends on the number of trailing zeros of the displacement. In practice
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/// the maximum effective range will be 1024 bytes, which is a 4-byte aligned
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/// instruction to a 4-byte aligned word.
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.arm
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.section .os1, "ax", %progbits
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.balign 1024
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.word 0
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.word 0
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.word 0
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.word 0
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dat1:
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.word 0
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dat2:
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.word 0
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.section .os2, "ax", %progbits
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.balign 1024
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.global _start
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.type _start, %function
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_start:
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/// adr r0, dat1
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.inst 0xe24f0008
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.reloc 0, R_ARM_ALU_PC_G0, dat1
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/// adr r0, dat2
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.inst 0xe24f0008
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.reloc 4, R_ARM_ALU_PC_G0, dat2
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/// adr r0, dat3
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.inst 0xe24f0008
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.reloc 8, R_ARM_ALU_PC_G0, dat3
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/// adr r0, dat4
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.inst 0xe24f0008
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.reloc 0xc, R_ARM_ALU_PC_G0, dat4
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.section .os3, "ax", %progbits
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.balign 1024
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.word 0
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.word 0
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.word 0
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.word 0
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dat3:
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.word 0
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dat4:
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.word 0
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.section .os4, "ax", %progbits
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.thumb
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.type tfunc, %function
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tfunc:
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bx lr
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.section .os5, "ax", %progbits
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.arm
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.type arm_func, %function
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arm_func:
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.balign 4
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/// adr r0, tfunc
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.inst 0xe24f0008
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.reloc 0, R_ARM_ALU_PC_G0, tfunc
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/// adr r0, afunc
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.inst 0xe24f0008
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.reloc 4, R_ARM_ALU_PC_G0, afunc
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bx lr
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.section .os6, "ax", %progbits
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.type afunc, %function
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.balign 4
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afunc:
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bx lr
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// CHECK: 00011410 <dat1>:
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// CHECK-NEXT: 11410: andeq r0, r0, r0
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// CHECK: 00011414 <dat2>:
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// CHECK-NEXT: 11414: andeq r0, r0, r0
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// CHECK: 00011800 <_start>:
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/// 0x11800 + 0x8 - 0x3f8 = 0x11410 = dat1
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// CHECK-NEXT: 11800: sub r0, pc, #1016
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/// 0x11804 + 0x8 - 0x3f8 = 0x11414 = dat2
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// CHECK-NEXT: 11804: sub r0, pc, #1016
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/// 0x11808 + 0x8 + 0x400 = 0x11c10 = dat3
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// CHECK-NEXT: 11808: add r0, pc, #1024
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/// 0x1180c + 0x8 + 0x400 = 0x11c14 = dat4
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// CHECK-NEXT: 1180c: add r0, pc, #1024
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// CHECK: 00011c10 <dat3>:
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// CHECK-NEXT: 11c10: andeq r0, r0, r0
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// CHECK: 00011c14 <dat4>:
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// CHECK-NEXT: 11c14: andeq r0, r0, r0
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// CHECK: 00011c18 <tfunc>:
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// CHECK-NEXT: 11c18: bx lr
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// CHECK: 00011c1c <arm_func>:
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/// 0x11c1c + 0x8 - 0xb = 11c19 = tfunc
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// CHECK-NEXT: 11c1c: sub r0, pc, #11
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/// 0x11c20 + 0x8 = 0x11c28 = afunc
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// CHECK-NEXT: 11c20: add r0, pc, #0
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// CHECK-NEXT: 11c24: bx lr
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// CHECK: 00011c28 <afunc>:
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// CHECK-NEXT: 11c28: bx lr
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@ -0,0 +1,29 @@
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// REQUIRES: arm
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// RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: not ld.lld -n %t.o -o %t 2>&1 | FileCheck %s
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.section .text.0, "ax", %progbits
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.thumb_func
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.balign 4
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low:
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bx lr
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nop
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nop
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.section .text.1, "ax", %progbits
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.global _start
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.arm
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_start:
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// CHECK: {{.*}}.s.tmp.o:(.text.1+0x0): relocation R_ARM_LDR_PC_G0 out of range: 4096 is not in [0, 4095]
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/// ldr r0, low - 4076
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.inst 0xe51f0ff4
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.reloc 0, R_ARM_LDR_PC_G0, low
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// CHECK: {{.*}}.s.tmp.o:(.text.1+0x4): relocation R_ARM_LDR_PC_G0 out of range: 4096 is not in [0, 4095]
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/// ldr r0, high + 4100
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.inst 0xe59f0ffc
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.reloc 4, R_ARM_LDR_PC_G0, high
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.section .text.2
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.thumb_func
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.balign 4
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high:
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bx lr
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@ -0,0 +1,170 @@
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// REQUIRES: arm
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// RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: llvm-objdump -d -r --triple=armv7a-none-eabi %t.o
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// RUN: echo "SECTIONS { \
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// RUN: .rodata.low 0x8012 : { *(.rodata.low) } \
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// RUN: .text.low 0x8f00 : { *(.text.low) } \
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// RUN: .text.neg 0x9000 : { *(.text.neg) } \
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// RUN: .text.pos 0x10000 : { *(.text.pos) } \
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// RUN: .text.high 0x10100 : { *(.text.high) } \
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// RUN: .data_high 0x1100f : { *(.data.high) } \
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// RUN: } " > %t.script
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// RUN: ld.lld -n --script %t.script %t.o -o %t
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// RUN: llvm-readobj --symbols %t | FileCheck %s --check-prefix=SYMS
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// RUN: llvm-objdump -d --no-show-raw-insn --triple=armv7a-none-eabi %t | FileCheck %s
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/// Test the various legal cases for the R_ARM_LDR_PC_G0 relocation
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/// Range is +- 4095 bytes
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/// The Thumb bit for function symbols is ignored
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.section .rodata.low, "a", %progbits
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dat1:
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.byte 0
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dat2:
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.byte 1
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dat3:
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.byte 2
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dat4:
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.byte 3
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.section .text.low, "ax", %progbits
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.balign 4
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.global target1
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.type target1, %function
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target1:
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bx lr
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.type target2, %function
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target2:
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bx lr
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.section .text.neg, "ax", %progbits
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.balign 4
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.global _start
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.type _start, %function
|
||||
_start:
|
||||
/// ldr r0, dat1
|
||||
.inst 0xe51f0008
|
||||
.reloc 0, R_ARM_LDR_PC_G0, dat1
|
||||
/// ldr r1, dat2
|
||||
.inst 0xe51f1008
|
||||
.reloc 4, R_ARM_LDR_PC_G0, dat2
|
||||
/// ldr r2, dat3
|
||||
.inst 0xe51f2008
|
||||
.reloc 8, R_ARM_LDR_PC_G0, dat3
|
||||
/// ldr r3, dat4
|
||||
.inst 0xe51f3008
|
||||
.reloc 0xc, R_ARM_LDR_PC_G0, dat4
|
||||
/// ldr r0, target1
|
||||
.inst 0xe51f0008
|
||||
.reloc 0x10, R_ARM_LDR_PC_G0, target1
|
||||
/// ldr r1, target2
|
||||
.inst 0xe51f1008
|
||||
.reloc 0x14, R_ARM_LDR_PC_G0, target2
|
||||
|
||||
.section .text.pos, "ax", %progbits
|
||||
.balign 4
|
||||
.global pos
|
||||
.type pos, %function
|
||||
pos:
|
||||
/// ldr r2, target3
|
||||
.inst 0xe51f2008
|
||||
.reloc 0, R_ARM_LDR_PC_G0, target3
|
||||
/// ldr r3, target4
|
||||
.inst 0xe51f3008
|
||||
.reloc 4, R_ARM_LDR_PC_G0, target4
|
||||
/// ldr r0, dat5
|
||||
.inst 0xe51f0008
|
||||
.reloc 8, R_ARM_LDR_PC_G0, dat5
|
||||
/// ldr r1, dat6
|
||||
.inst 0xe51f1008
|
||||
.reloc 0xc, R_ARM_LDR_PC_G0, dat6
|
||||
/// ldr r2, dat7
|
||||
.inst 0xe51f2008
|
||||
.reloc 0x10, R_ARM_LDR_PC_G0, dat7
|
||||
/// ldr r3, dat8
|
||||
.inst 0xe51f3008
|
||||
.reloc 0x14, R_ARM_LDR_PC_G0, dat8
|
||||
|
||||
/// positive addend in instruction, all others are -4 (PC bias)
|
||||
///ldr r4, dat5 + 8
|
||||
.inst 0xe59f4000
|
||||
.reloc 0x18, R_ARM_LDR_PC_G0, dat5
|
||||
|
||||
.section .text.high, "ax", %progbits
|
||||
.balign 4
|
||||
.type target3, %function
|
||||
.global target3
|
||||
target3:
|
||||
bx lr
|
||||
.thumb_func
|
||||
target4:
|
||||
bx lr
|
||||
|
||||
.section .data.high, "aw", %progbits
|
||||
dat5:
|
||||
.byte 0
|
||||
dat6:
|
||||
.byte 1
|
||||
dat7:
|
||||
.byte 2
|
||||
dat8:
|
||||
.byte 3
|
||||
|
||||
// SYMS: Name: dat1
|
||||
// SYMS-NEXT: Value: 0x8012
|
||||
// SYMS: Name: dat2
|
||||
// SYMS-NEXT: Value: 0x8013
|
||||
// SYMS: Name: dat3
|
||||
// SYMS-NEXT: Value: 0x8014
|
||||
// SYMS: Name: dat4
|
||||
// SYMS-NEXT: Value: 0x8015
|
||||
|
||||
// CHECK: 00008f00 <target1>:
|
||||
// CHECK-NEXT: 8f00: bx lr
|
||||
|
||||
// CHECK: 00008f04 <target2>:
|
||||
// CHECK-NEXT: 8f04: bx lr
|
||||
|
||||
// CHECK: 00009000 <_start>:
|
||||
/// 0x9000 + 0x8 - 0xff6 = 0x8012
|
||||
// CHECK-NEXT: 9000: ldr r0, [pc, #-4086]
|
||||
/// 0x9004 + 0x8 - 0xff9 = 0x8013
|
||||
// CHECK-NEXT: 9004: ldr r1, [pc, #-4089]
|
||||
/// 0x9008 + 0x8 - 0xffc = 0x8014
|
||||
// CHECK-NEXT: 9008: ldr r2, [pc, #-4092]
|
||||
/// 0x900c + 0x8 - 0xfff = 0x8015
|
||||
// CHECK-NEXT: 900c: ldr r3, [pc, #-4095]
|
||||
/// 0x9010 + 0x8 - 0x118 = 0x8f00
|
||||
// CHECK-NEXT: 9010: ldr r0, [pc, #-280]
|
||||
/// 0x9014 + 0x8 - 0x118 = 0x8f04
|
||||
// CHECK-NEXT: 9014: ldr r1, [pc, #-280]
|
||||
///
|
||||
// CHECK: 00010000 <pos>:
|
||||
/// 0x10000 + 0x8 + 0xf8 = 0x10100
|
||||
// CHECK-NEXT: 10000: ldr r2, [pc, #248]
|
||||
/// 0x10004 + 0x8 + 0xf8 = 0x10104
|
||||
// CHECK-NEXT: 10004: ldr r3, [pc, #248]
|
||||
/// 0x10008 + 0x8 + 0xfff = 0x1100f
|
||||
// CHECK-NEXT: 10008: ldr r0, [pc, #4095]
|
||||
/// 0x1000c + 0x8 + 0xffc = 0x11010
|
||||
// CHECK-NEXT: 1000c: ldr r1, [pc, #4092]
|
||||
/// 0x10010 + 0x8 + 0xff9 = 0x11011
|
||||
// CHECK-NEXT: 10010: ldr r2, [pc, #4089]
|
||||
/// 0x10014 + 0x8 + 0xff6 = 0x11012
|
||||
// CHECK-NEXT: 10014: ldr r3, [pc, #4086]
|
||||
/// 0x10018 + 0x8 + 0xff7 = 0x11017 = dat5 + 8
|
||||
// CHECK-NEXT: 10018: ldr r4, [pc, #4087]
|
||||
|
||||
// CHECK: 00010100 <target3>:
|
||||
// CHECK-NEXT: 10100: bx lr
|
||||
|
||||
// CHECK: 00010104 <target4>:
|
||||
// CHECK-NEXT: 10104: bx lr
|
||||
|
||||
// SYMS: Name: dat5
|
||||
// SYMS-NEXT: Value: 0x1100F
|
||||
// SYMS: Name: dat6
|
||||
// SYMS-NEXT: Value: 0x11010
|
||||
// SYMS: Name: dat7
|
||||
// SYMS-NEXT: Value: 0x11011
|
||||
// SYMS: Name: dat8
|
||||
// SYMS-NEXT: Value: 0x11012
|
||||
Loading…
Reference in New Issue