forked from OSchip/llvm-project
[InstCombine] try harder to narrow bitwise logic with cast operands
This works with any logic + extend: https://alive2.llvm.org/ce/z/vzsqQD The motivating case is from issue #56294, but that's still not optimal (it should simplify completely).
This commit is contained in:
Sanjay Patel
parent
35e8179c47
commit
28ad5dc3f7
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@ -1430,12 +1430,34 @@ Instruction *InstCombinerImpl::foldCastedBitwiseLogic(BinaryOperator &I) {
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if (!Cast1)
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return nullptr;
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// Both operands of the logic operation are casts. The casts must be of the
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// same type for reduction.
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auto CastOpcode = Cast0->getOpcode();
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if (CastOpcode != Cast1->getOpcode() || SrcTy != Cast1->getSrcTy())
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// Both operands of the logic operation are casts. The casts must be the
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// same kind for reduction.
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Instruction::CastOps CastOpcode = Cast0->getOpcode();
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if (CastOpcode != Cast1->getOpcode())
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return nullptr;
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// If the source types do not match, but the casts are matching extends, we
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// can still narrow the logic op.
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if (SrcTy != Cast1->getSrcTy()) {
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Value *X, *Y;
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if (match(Cast0, m_OneUse(m_ZExtOrSExt(m_Value(X)))) &&
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match(Cast1, m_OneUse(m_ZExtOrSExt(m_Value(Y))))) {
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// Cast the narrower source to the wider source type.
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unsigned XNumBits = X->getType()->getScalarSizeInBits();
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unsigned YNumBits = Y->getType()->getScalarSizeInBits();
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if (XNumBits < YNumBits)
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X = Builder.CreateCast(CastOpcode, X, Y->getType());
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else
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Y = Builder.CreateCast(CastOpcode, Y, X->getType());
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// Do the logic op in the intermediate width, then widen more.
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Value *NarrowLogic = Builder.CreateBinOp(LogicOpc, X, Y);
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return CastInst::Create(CastOpcode, NarrowLogic, DestTy);
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}
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// Give up for other cast opcodes.
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return nullptr;
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}
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Value *Cast0Src = Cast0->getOperand(0);
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Value *Cast1Src = Cast1->getOperand(0);
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@ -4209,9 +4209,9 @@ define i32 @trunc_trunc_xor_uses(i65 %x, i65 %y) {
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define i16 @and_zext_zext(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@and_zext_zext
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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; CHECK-NEXT: [[ZX:%.*]] = zext i8 [[X]] to i16
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; CHECK-NEXT: [[ZY:%.*]] = zext i4 [[Y]] to i16
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; CHECK-NEXT: [[R:%.*]] = and i16 [[ZX]], [[ZY]]
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; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[Y]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%zx = zext i8 %x to i16
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@ -4223,9 +4223,9 @@ define i16 @and_zext_zext(i8 %x, i4 %y) {
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define i16 @or_zext_zext(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@or_zext_zext
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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; CHECK-NEXT: [[ZX:%.*]] = zext i8 [[X]] to i16
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; CHECK-NEXT: [[ZY:%.*]] = zext i4 [[Y]] to i16
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; CHECK-NEXT: [[R:%.*]] = or i16 [[ZY]], [[ZX]]
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; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[Y]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%zx = zext i8 %x to i16
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@ -4237,9 +4237,9 @@ define i16 @or_zext_zext(i8 %x, i4 %y) {
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define <2 x i16> @xor_zext_zext(<2 x i8> %x, <2 x i4> %y) {
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; CHECK-LABEL: define {{[^@]+}}@xor_zext_zext
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; CHECK-SAME: (<2 x i8> [[X:%.*]], <2 x i4> [[Y:%.*]]) {
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; CHECK-NEXT: [[ZX:%.*]] = zext <2 x i8> [[X]] to <2 x i16>
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; CHECK-NEXT: [[ZY:%.*]] = zext <2 x i4> [[Y]] to <2 x i16>
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; CHECK-NEXT: [[R:%.*]] = xor <2 x i16> [[ZX]], [[ZY]]
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; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i4> [[Y]] to <2 x i8>
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; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i8> [[TMP1]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[R]]
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;
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%zx = zext <2 x i8> %x to <2 x i16>
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@ -4251,9 +4251,9 @@ define <2 x i16> @xor_zext_zext(<2 x i8> %x, <2 x i4> %y) {
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define i16 @and_sext_sext(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@and_sext_sext
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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; CHECK-NEXT: [[SX:%.*]] = sext i8 [[X]] to i16
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; CHECK-NEXT: [[SY:%.*]] = sext i4 [[Y]] to i16
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; CHECK-NEXT: [[R:%.*]] = and i16 [[SY]], [[SX]]
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; CHECK-NEXT: [[TMP1:%.*]] = sext i4 [[Y]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP2]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%sx = sext i8 %x to i16
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@ -4265,9 +4265,9 @@ define i16 @and_sext_sext(i8 %x, i4 %y) {
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define i16 @or_sext_sext(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@or_sext_sext
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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; CHECK-NEXT: [[SX:%.*]] = sext i8 [[X]] to i16
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; CHECK-NEXT: [[SY:%.*]] = sext i4 [[Y]] to i16
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; CHECK-NEXT: [[R:%.*]] = or i16 [[SX]], [[SY]]
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; CHECK-NEXT: [[TMP1:%.*]] = sext i4 [[Y]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP2]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%sx = sext i8 %x to i16
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@ -4279,9 +4279,9 @@ define i16 @or_sext_sext(i8 %x, i4 %y) {
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define i16 @xor_sext_sext(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@xor_sext_sext
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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; CHECK-NEXT: [[SX:%.*]] = sext i8 [[X]] to i16
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; CHECK-NEXT: [[SY:%.*]] = sext i4 [[Y]] to i16
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; CHECK-NEXT: [[R:%.*]] = xor i16 [[SX]], [[SY]]
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; CHECK-NEXT: [[TMP1:%.*]] = sext i4 [[Y]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[TMP1]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP2]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%sx = sext i8 %x to i16
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@ -4290,6 +4290,8 @@ define i16 @xor_sext_sext(i8 %x, i4 %y) {
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ret i16 %r
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}
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; negative test - mismatched casts
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define i16 @and_zext_sext(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@and_zext_sext
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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@ -4304,6 +4306,8 @@ define i16 @and_zext_sext(i8 %x, i4 %y) {
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ret i16 %r
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}
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; negative test - don't create an extra instruction
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define i32 @and_zext_zext_use1(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@and_zext_zext_use1
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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@ -4320,6 +4324,8 @@ define i32 @and_zext_zext_use1(i8 %x, i4 %y) {
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ret i32 %r
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}
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; negative test - don't create an extra instruction
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define i32 @or_sext_sext_use1(i8 %x, i4 %y) {
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; CHECK-LABEL: define {{[^@]+}}@or_sext_sext_use1
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; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) {
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@ -4335,3 +4341,21 @@ define i32 @or_sext_sext_use1(i8 %x, i4 %y) {
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%r = or i32 %sx, %sy
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ret i32 %r
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}
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define i1 @PR56294(i8 %x) {
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; CHECK-LABEL: define {{[^@]+}}@PR56294
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; CHECK-SAME: (i8 [[X:%.*]]) {
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; CHECK-NEXT: [[T2:%.*]] = icmp eq i8 [[X]], 2
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; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[T2]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]
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; CHECK-NEXT: [[T7:%.*]] = icmp ne i8 [[TMP2]], 0
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; CHECK-NEXT: ret i1 [[T7]]
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;
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%t2 = icmp eq i8 %x, 2
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%t3 = and i8 %x, 1
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%t4 = zext i1 %t2 to i32
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%t5 = zext i8 %t3 to i32
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%t6 = and i32 %t4, %t5
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%t7 = icmp ne i32 %t6, 0
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ret i1 %t7
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}
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