diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f33965b50459..399be7abc9e6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1166,7 +1166,7 @@ bool RISCVTargetLowering::isCheapToSpeculateCtlz() const {
   return Subtarget.hasStdExtZbb();
 }
 
-bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
+bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
   EVT VT = Y.getValueType();
 
   // FIXME: Support vectors once we have tests.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 4ccfcbc50f7c..a2d3c74ed5fd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -315,7 +315,7 @@ public:
   bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
   bool isCheapToSpeculateCttz() const override;
   bool isCheapToSpeculateCtlz() const override;
-  bool hasAndNot(SDValue Y) const override;
+  bool hasAndNotCompare(SDValue Y) const override;
   bool shouldSinkOperands(Instruction *I,
                           SmallVectorImpl<Use *> &Ops) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
index b2994fcdaf81..452de04563f0 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
@@ -568,8 +568,7 @@ define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: andn_seqz_i32:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    and a0, a0, a1
-; RV32ZBB-NEXT:    xor a0, a0, a1
+; RV32ZBB-NEXT:    andn a0, a1, a0
 ; RV32ZBB-NEXT:    seqz a0, a0
 ; RV32ZBB-NEXT:    ret
 ;
@@ -625,8 +624,7 @@ define i1 @andn_snez_i32(i32 %a, i32 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: andn_snez_i32:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    and a0, a0, a1
-; RV32ZBB-NEXT:    xor a0, a0, a1
+; RV32ZBB-NEXT:    andn a0, a1, a0
 ; RV32ZBB-NEXT:    snez a0, a0
 ; RV32ZBB-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
index be08a3ee8b1f..dc9c37b2ba6c 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
@@ -639,8 +639,7 @@ define i1 @andn_seqz_i32(i32 signext %a, i32 signext %b) nounwind {
 ;
 ; RV64ZBB-LABEL: andn_seqz_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
@@ -665,8 +664,7 @@ define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: andn_seqz_i64:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
@@ -691,8 +689,7 @@ define i1 @andn_snez_i32(i32 signext %a, i32 signext %b) nounwind {
 ;
 ; RV64ZBB-LABEL: andn_snez_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
@@ -717,8 +714,7 @@ define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: andn_snez_i64:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
 ;