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[RISCV] Override hasAndNotCompare to use more andn when have Zbb extension. 

Enable transform (X & Y) == Y ---> (~X & Y) == 0 and (X & Y) != Y ---> (~X & Y) != 0 when have Zbb extension to use more andn instruction.

Differential Revision: https://reviews.llvm.org/D115922
This commit is contained in:
jacquesguan 2021-12-17 17:28:27 +08:00
parent ee5d5e19f9
commit 28a3e7dea2
4 changed files with 8 additions and 14 deletions
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2
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -1166,7 +1166,7 @@ bool RISCVTargetLowering::isCheapToSpeculateCtlz() const {
return Subtarget.hasStdExtZbb();
}
bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
EVT VT = Y.getValueType();
// FIXME: Support vectors once we have tests.

2
llvm/lib/Target/RISCV/RISCVISelLowering.h
View File

@ -315,7 +315,7 @@ public:
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override;
bool hasAndNot(SDValue Y) const override;
bool hasAndNotCompare(SDValue Y) const override;
bool shouldSinkOperands(Instruction *I,
SmallVectorImpl<Use *> &Ops) const override;
bool isFPImmLegal(const APFloat &Imm, EVT VT,

6
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
View File

@ -568,8 +568,7 @@ define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {
;
; RV32ZBB-LABEL: andn_seqz_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: xor a0, a0, a1
; RV32ZBB-NEXT: andn a0, a1, a0
; RV32ZBB-NEXT: seqz a0, a0
; RV32ZBB-NEXT: ret
;
@ -625,8 +624,7 @@ define i1 @andn_snez_i32(i32 %a, i32 %b) nounwind {
;
; RV32ZBB-LABEL: andn_snez_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: xor a0, a0, a1
; RV32ZBB-NEXT: andn a0, a1, a0
; RV32ZBB-NEXT: snez a0, a0
; RV32ZBB-NEXT: ret
;

12
llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
View File

@ -639,8 +639,7 @@ define i1 @andn_seqz_i32(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBB-LABEL: andn_seqz_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: andn a0, a1, a0
; RV64ZBB-NEXT: seqz a0, a0
; RV64ZBB-NEXT: ret
;
@ -665,8 +664,7 @@ define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
;
; RV64ZBB-LABEL: andn_seqz_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: andn a0, a1, a0
; RV64ZBB-NEXT: seqz a0, a0
; RV64ZBB-NEXT: ret
;
@ -691,8 +689,7 @@ define i1 @andn_snez_i32(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBB-LABEL: andn_snez_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: andn a0, a1, a0
; RV64ZBB-NEXT: snez a0, a0
; RV64ZBB-NEXT: ret
;
@ -717,8 +714,7 @@ define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
;
; RV64ZBB-LABEL: andn_snez_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: xor a0, a0, a1
; RV64ZBB-NEXT: andn a0, a1, a0
; RV64ZBB-NEXT: snez a0, a0
; RV64ZBB-NEXT: ret
;