forked from OSchip/llvm-project
parent
4cadd4afa0
commit
287c4e1762
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@ -1291,7 +1291,6 @@ isConditionalTransfer (const MachineInstr *MI) const {
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}
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bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
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const HexagonRegisterInfo& QRI = getRegisterInfo();
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switch (MI->getOpcode())
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{
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default: return false;
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