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[Aarch64] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans. 

Differential Revision: https://reviews.llvm.org/D89551
This commit is contained in:
Paul C. Anagnostopoulos 2020-10-15 18:42:27 -04:00
parent 627c01bee0
commit 2871c6c93f
1 changed files with 6 additions and 6 deletions
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12
llvm/lib/Target/AArch64/SVEInstrFormats.td
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@ -5653,7 +5653,7 @@ class sve_int_rdffr_pred<bit s, string asm>
let Inst{4} = 0;
let Inst{3-0} = Pd;
let Defs = !if(!eq (s, 1), [NZCV], []);
let Defs = !if(s, [NZCV], []);
let Uses = [FFR];
}
@ -6155,8 +6155,8 @@ class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
let Inst{4-0} = Zt;
let mayLoad = 1;
let Uses = !if(!eq(nf, 1), [FFR], []);
let Defs = !if(!eq(nf, 1), [FFR], []);
let Uses = !if(nf, [FFR], []);
let Defs = !if(nf, [FFR], []);
}
multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
@ -6358,8 +6358,8 @@ class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
let Inst{4-0} = Zt;
let mayLoad = 1;
let Uses = !if(!eq(ff, 1), [FFR], []);
let Defs = !if(!eq(ff, 1), [FFR], []);
let Uses = !if(ff, [FFR], []);
let Defs = !if(ff, [FFR], []);
}
multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
@ -7361,7 +7361,7 @@ class sve_int_brkn<bit S, string asm>
let Inst{3-0} = Pdm;
let Constraints = "$Pdm = $_Pdm";
let Defs = !if(!eq (S, 0b1), [NZCV], []);
let Defs = !if(S, [NZCV], []);
}
multiclass sve_int_brkn<bits<1> opc, string asm, SDPatternOperator op> {