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Fix PR 17372: Emitting PLD for stack address for ARM Thumb2 

t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.

llvm-svn: 191441
This commit is contained in:
Weiming Zhao 2013-09-26 17:25:10 +00:00
parent cea1596205
commit 286304a317
2 changed files with 29 additions and 0 deletions
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7
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -334,6 +334,7 @@ negativeOffsetOpcode(unsigned opcode)
case ARM::t2STRi12: return ARM::t2STRi8; case ARM::t2STRi12: return ARM::t2STRi8;
case ARM::t2STRBi12: return ARM::t2STRBi8; case ARM::t2STRBi12: return ARM::t2STRBi8;
case ARM::t2STRHi12: return ARM::t2STRHi8; case ARM::t2STRHi12: return ARM::t2STRHi8;
case ARM::t2PLDi12: return ARM::t2PLDi8;
case ARM::t2LDRi8: case ARM::t2LDRi8:
case ARM::t2LDRHi8: case ARM::t2LDRHi8:
@ -343,6 +344,7 @@ negativeOffsetOpcode(unsigned opcode)
case ARM::t2STRi8: case ARM::t2STRi8:
case ARM::t2STRBi8: case ARM::t2STRBi8:
case ARM::t2STRHi8: case ARM::t2STRHi8:
case ARM::t2PLDi8:
return opcode; return opcode;
default: default:
@ -364,6 +366,7 @@ positiveOffsetOpcode(unsigned opcode)
case ARM::t2STRi8: return ARM::t2STRi12; case ARM::t2STRi8: return ARM::t2STRi12;
case ARM::t2STRBi8: return ARM::t2STRBi12; case ARM::t2STRBi8: return ARM::t2STRBi12;
case ARM::t2STRHi8: return ARM::t2STRHi12; case ARM::t2STRHi8: return ARM::t2STRHi12;
case ARM::t2PLDi8: return ARM::t2PLDi12;
case ARM::t2LDRi12: case ARM::t2LDRi12:
case ARM::t2LDRHi12: case ARM::t2LDRHi12:
@ -373,6 +376,7 @@ positiveOffsetOpcode(unsigned opcode)
case ARM::t2STRi12: case ARM::t2STRi12:
case ARM::t2STRBi12: case ARM::t2STRBi12:
case ARM::t2STRHi12: case ARM::t2STRHi12:
case ARM::t2PLDi12:
return opcode; return opcode;
default: default:
@ -394,6 +398,7 @@ immediateOffsetOpcode(unsigned opcode)
case ARM::t2STRs: return ARM::t2STRi12; case ARM::t2STRs: return ARM::t2STRi12;
case ARM::t2STRBs: return ARM::t2STRBi12; case ARM::t2STRBs: return ARM::t2STRBi12;
case ARM::t2STRHs: return ARM::t2STRHi12; case ARM::t2STRHs: return ARM::t2STRHi12;
case ARM::t2PLDs: return ARM::t2PLDi12;
case ARM::t2LDRi12: case ARM::t2LDRi12:
case ARM::t2LDRHi12: case ARM::t2LDRHi12:
@ -403,6 +408,7 @@ immediateOffsetOpcode(unsigned opcode)
case ARM::t2STRi12: case ARM::t2STRi12:
case ARM::t2STRBi12: case ARM::t2STRBi12:
case ARM::t2STRHi12: case ARM::t2STRHi12:
case ARM::t2PLDi12:
case ARM::t2LDRi8: case ARM::t2LDRi8:
case ARM::t2LDRHi8: case ARM::t2LDRHi8:
case ARM::t2LDRBi8: case ARM::t2LDRBi8:
@ -411,6 +417,7 @@ immediateOffsetOpcode(unsigned opcode)
case ARM::t2STRi8: case ARM::t2STRi8:
case ARM::t2STRBi8: case ARM::t2STRBi8:
case ARM::t2STRHi8: case ARM::t2STRHi8:
case ARM::t2PLDi8:
return opcode; return opcode;
default: default:

22
llvm/test/CodeGen/ARM/prefetch-thumb.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2
; TODO: This test case will be merged back into prefetch.ll when ARM mode issue is solved.
declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
define void @t6() {
entry:
;ARM: t6:
;ARM: pld [sp]
;ARM: pld [sp, #50]
;THUMB2: t6:
;THUMB2: pld [sp]
;THUMB2: pld [sp, #50]
%red = alloca [100 x i8], align 1
%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0
%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50
call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
ret void
}