forked from OSchip/llvm-project
[AArch64][GlobalISel] Add support for selection of s8:fpr = G_UNMERGE <8 x s8>
This commit is contained in:
Amara Emerson
parent
25ec252537
commit
284006079e
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@ -3830,6 +3830,10 @@ static bool getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg,
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// Choose a lane copy opcode and subregister based off of the size of the
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// vector's elements.
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switch (EltSize) {
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case 8:
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CopyOpc = AArch64::CPYi8;
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ExtractSubReg = AArch64::bsub;
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break;
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case 16:
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CopyOpc = AArch64::CPYi16;
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ExtractSubReg = AArch64::hsub;
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@ -1,39 +1,8 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mattr=-fullfp16 -mtriple=aarch64-- \
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# RUN: -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
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--- |
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define <2 x double> @test_v2s64_unmerge(<2 x double> %a) {
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ret <2 x double> %a
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}
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define <4 x float> @test_v4s32_unmerge(<4 x float> %a) {
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ret <4 x float> %a
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}
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define <2 x half> @test_v2s16_unmerge(<2 x half> %a) {
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ret <2 x half> %a
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}
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define <4 x half> @test_v4s16_unmerge(<4 x half> %a) {
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ret <4 x half> %a
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}
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define <8 x half> @test_v8s16_unmerge(<8 x half> %a) {
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ret <8 x half> %a
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}
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define <2 x float> @test_vecsplit_2v2s32_v4s32(<4 x float> %a) {
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ret <2 x float> undef
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}
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define <2 x half> @test_vecsplit_2v2s16_v4s16(<4 x half> %a) {
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ret <2 x half> undef
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}
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define void @test_s128(i128 %p) { ret void }
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...
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---
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name: test_v2s64_unmerge
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alignment: 4
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@ -46,14 +15,23 @@ registers:
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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body: |
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bb.1 (%ir-block.0):
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: test_v2s64_unmerge
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; CHECK-LABEL: name: test_v2s64_unmerge
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[CPYi64_]], %subreg.dsub
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; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: $q0 = COPY [[INSvi64lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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; Since 2 * 64 = 128, we can just directly copy.
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; CHECK: %2:fpr64 = COPY %0.dsub
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; CHECK: %3:fpr64 = CPYi64 %0, 1
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%2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
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%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
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@ -74,16 +52,31 @@ registers:
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- { id: 4, class: fpr }
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- { id: 5, class: fpr }
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body: |
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bb.1 (%ir-block.0):
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: test_v4s32_unmerge
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; CHECK-LABEL: name: test_v4s32_unmerge
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
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; CHECK: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[COPY]], 1
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; CHECK: [[CPYi32_1:%[0-9]+]]:fpr32 = CPYi32 [[COPY]], 2
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; CHECK: [[CPYi32_2:%[0-9]+]]:fpr32 = CPYi32 [[COPY]], 3
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.ssub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[CPYi32_]], %subreg.ssub
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; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[CPYi32_1]], %subreg.ssub
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; CHECK: [[INSvi32lane1:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane]], 2, [[INSERT_SUBREG2]], 0
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; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[CPYi32_2]], %subreg.ssub
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; CHECK: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0
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; CHECK: $q0 = COPY [[INSvi32lane2]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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; Since 4 * 32 = 128, we can just directly copy.
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; CHECK: %2:fpr32 = COPY %0.ssub
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; CHECK: %3:fpr32 = CPYi32 %0, 1
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; CHECK: %4:fpr32 = CPYi32 %0, 2
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; CHECK: %5:fpr32 = CPYi32 %0, 3
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%2:fpr(s32), %3:fpr(s32), %4:fpr(s32), %5:fpr(s32) = G_UNMERGE_VALUES %0(<4 x s32>)
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%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %4(s32), %5(s32)
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@ -103,34 +96,35 @@ registers:
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- { id: 4, class: fpr }
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- { id: 5, class: fpr }
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body: |
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bb.1 (%ir-block.0):
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bb.1:
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liveins: $s0
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; CHECK-LABEL: name: test_v2s16_unmerge
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; CHECK: liveins: $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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%0:fpr(<2 x s16>) = COPY $s0
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; Since 2 * 16 != 128, we need to widen using implicit defs.
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; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
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; expects a lane > 0.
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
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; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
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%2:fpr(s16), %3:fpr(s16) = G_UNMERGE_VALUES %0(<2 x s16>)
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.hsub
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; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[CPYi16_]], %subreg.hsub
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; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG2]], 0
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[INSvi16lane]].ssub
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; CHECK: $s0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(<2 x s16>) = COPY $s0
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; Since 2 * 16 != 128, we need to widen using implicit defs.
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; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
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; expects a lane > 0.
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%2:fpr(s16), %3:fpr(s16) = G_UNMERGE_VALUES %0(<2 x s16>)
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%1:fpr(<2 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16)
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; CHECK: $s0 = COPY [[COPY2]]
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$s0 = COPY %1(<2 x s16>)
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; CHECK: RET_ReallyLR implicit $s0
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RET_ReallyLR implicit $s0
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...
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---
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@ -147,24 +141,40 @@ registers:
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- { id: 4, class: fpr }
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- { id: 5, class: fpr }
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body: |
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bb.1 (%ir-block.0):
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bb.1:
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liveins: $d0
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; CHECK-LABEL: name: test_v4s16_unmerge
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; CHECK-LABEL: name: test_v4s16_unmerge
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
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; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
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; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
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; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG1]], 2
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; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG2]], 3
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; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY1]], %subreg.hsub
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; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[CPYi16_]], %subreg.hsub
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; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
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; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[CPYi16_1]], %subreg.hsub
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; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
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; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[CPYi16_2]], %subreg.hsub
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; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
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; CHECK: $d0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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; Since 4 * 16 != 128, we need to widen using implicit defs.
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; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
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; expects a lane > 0.
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; CHECK-DAG: [[IMPDEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INS_SHARED:%[0-9]+]]:fpr128 = INSERT_SUBREG [[IMPDEF1]], %0, %subreg.dsub
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; CHECK: [[IMPDEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INS2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[IMPDEF2]], %0, %subreg.dsub
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; CHECK: [[IMPDEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INS3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[IMPDEF3]], %0, %subreg.dsub
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; CHECK: %2:fpr16 = COPY [[INS_SHARED]].hsub
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; CHECK: %3:fpr16 = CPYi16 [[INS_SHARED]], 1
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; CHECK: %4:fpr16 = CPYi16 [[INS2]], 2
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; CHECK: %5:fpr16 = CPYi16 [[INS3]], 3
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%2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
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%1:fpr(<4 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16), %5(s16)
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@ -189,20 +199,47 @@ registers:
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- { id: 8, class: fpr }
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- { id: 9, class: fpr }
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body: |
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bb.1 (%ir-block.0):
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: test_v8s16_unmerge
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; CHECK-LABEL: name: test_v8s16_unmerge
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
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; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 2
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; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 3
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; CHECK: [[CPYi16_3:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 4
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; CHECK: [[CPYi16_4:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 5
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; CHECK: [[CPYi16_5:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 6
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; CHECK: [[CPYi16_6:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 7
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.hsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[CPYi16_]], %subreg.hsub
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; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[CPYi16_1]], %subreg.hsub
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; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
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; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[CPYi16_2]], %subreg.hsub
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; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
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; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[CPYi16_3]], %subreg.hsub
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; CHECK: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
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; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[CPYi16_4]], %subreg.hsub
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; CHECK: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
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; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[CPYi16_5]], %subreg.hsub
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; CHECK: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
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; CHECK: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[CPYi16_6]], %subreg.hsub
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; CHECK: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
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; CHECK: $q0 = COPY [[INSvi16lane6]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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; Since 8 * 16 = 128, we can just directly copy.
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; CHECK: %2:fpr16 = COPY %0.hsub
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; CHECK: %3:fpr16 = CPYi16 %0, 1
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; CHECK: %4:fpr16 = CPYi16 %0, 2
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; CHECK: %5:fpr16 = CPYi16 %0, 3
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; CHECK: %6:fpr16 = CPYi16 %0, 4
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; CHECK: %7:fpr16 = CPYi16 %0, 5
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; CHECK: %8:fpr16 = CPYi16 %0, 6
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; CHECK: %9:fpr16 = CPYi16 %0, 7
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%2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
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%1:fpr(<8 x s16>) = G_BUILD_VECTOR %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16)
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@ -210,13 +247,68 @@ body: |
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v8s8_unmerge
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
|
||||
liveins: $q0
|
||||
; CHECK-LABEL: name: test_v8s8_unmerge
|
||||
; CHECK: liveins: $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
|
||||
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
||||
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
|
||||
; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
||||
; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
|
||||
; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
||||
; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY]], %subreg.dsub
|
||||
; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
||||
; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[COPY]], %subreg.dsub
|
||||
; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
||||
; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[COPY]], %subreg.dsub
|
||||
; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
||||
; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[COPY]], %subreg.dsub
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr8 = COPY [[INSERT_SUBREG]].bsub
|
||||
; CHECK: [[CPYi8_:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG]], 1
|
||||
; CHECK: [[CPYi8_1:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG1]], 2
|
||||
; CHECK: [[CPYi8_2:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG2]], 3
|
||||
; CHECK: [[CPYi8_3:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG3]], 4
|
||||
; CHECK: [[CPYi8_4:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG4]], 5
|
||||
; CHECK: [[CPYi8_5:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG5]], 6
|
||||
; CHECK: [[CPYi8_6:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG6]], 7
|
||||
; CHECK: $b0 = COPY [[COPY1]]
|
||||
; CHECK: $b1 = COPY [[CPYi8_]]
|
||||
; CHECK: $b2 = COPY [[CPYi8_1]]
|
||||
; CHECK: $b3 = COPY [[CPYi8_2]]
|
||||
; CHECK: $b4 = COPY [[CPYi8_3]]
|
||||
; CHECK: $b5 = COPY [[CPYi8_4]]
|
||||
; CHECK: $b6 = COPY [[CPYi8_5]]
|
||||
; CHECK: $b7 = COPY [[CPYi8_6]]
|
||||
; CHECK: RET_ReallyLR implicit $d0
|
||||
%0:fpr(<8 x s8>) = COPY $d0
|
||||
%2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8) = G_UNMERGE_VALUES %0(<8 x s8>)
|
||||
$b0 = COPY %2
|
||||
$b1 = COPY %3
|
||||
$b2 = COPY %4
|
||||
$b3 = COPY %5
|
||||
$b4 = COPY %6
|
||||
$b5 = COPY %7
|
||||
$b6 = COPY %8
|
||||
$b7 = COPY %9
|
||||
RET_ReallyLR implicit $d0
|
||||
...
|
||||
---
|
||||
name: test_vecsplit_2v2s32_v4s32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
bb.1:
|
||||
liveins: $q0
|
||||
; CHECK-LABEL: name: test_vecsplit_2v2s32_v4s32
|
||||
; CHECK: liveins: $q0
|
||||
|
|
@ -239,7 +331,7 @@ legalized: true
|
|||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
bb.1:
|
||||
liveins: $d0
|
||||
; CHECK-LABEL: name: test_vecsplit_2v2s16_v4s16
|
||||
; CHECK: liveins: $d0
|
||||
|
|
@ -266,6 +358,14 @@ tracksRegLiveness: true
|
|||
body: |
|
||||
bb.1:
|
||||
liveins: $q0
|
||||
; CHECK-LABEL: name: test_s128
|
||||
; CHECK: liveins: $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
|
||||
; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1
|
||||
; CHECK: $d0 = COPY [[COPY1]]
|
||||
; CHECK: $d1 = COPY [[CPYi64_]]
|
||||
; CHECK: RET_ReallyLR implicit $d0, implicit $d1
|
||||
%0:fpr(s128) = COPY $q0
|
||||
%1:fpr(s64), %2:fpr(s64) = G_UNMERGE_VALUES %0(s128)
|
||||
$d0 = COPY %1(s64)
|
||||
|
|
|
|||
Loading…
Reference in New Issue