forked from OSchip/llvm-project
[TableGen] Add a non-default constructor to CodeGenSchedClass and use it via emplace_back to create new SchedClasses instead of using resize(size+1)
llvm-svn: 328183
This commit is contained in:
parent
deb7e4e009
commit
281a19cf7b
|
@ -557,10 +557,9 @@ unsigned CodeGenSchedModels::findOrInsertRW(ArrayRef<unsigned> Seq,
|
||||||
void CodeGenSchedModels::collectSchedClasses() {
|
void CodeGenSchedModels::collectSchedClasses() {
|
||||||
|
|
||||||
// NoItinerary is always the first class at Idx=0
|
// NoItinerary is always the first class at Idx=0
|
||||||
SchedClasses.resize(1);
|
assert(SchedClasses.empty() && "Expected empty sched class");
|
||||||
SchedClasses.back().Index = 0;
|
SchedClasses.emplace_back(0, "NoInstrModel",
|
||||||
SchedClasses.back().Name = "NoInstrModel";
|
Records.getDef("NoItinerary"));
|
||||||
SchedClasses.back().ItinClassDef = Records.getDef("NoItinerary");
|
|
||||||
SchedClasses.back().ProcIndices.push_back(0);
|
SchedClasses.back().ProcIndices.push_back(0);
|
||||||
|
|
||||||
// Create a SchedClass for each unique combination of itinerary class and
|
// Create a SchedClass for each unique combination of itinerary class and
|
||||||
|
@ -572,9 +571,7 @@ void CodeGenSchedModels::collectSchedClasses() {
|
||||||
findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
|
findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
|
||||||
|
|
||||||
// ProcIdx == 0 indicates the class applies to all processors.
|
// ProcIdx == 0 indicates the class applies to all processors.
|
||||||
IdxVec ProcIndices(1, 0);
|
unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0});
|
||||||
|
|
||||||
unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
|
|
||||||
InstrClassMap[Inst->TheDef] = SCIdx;
|
InstrClassMap[Inst->TheDef] = SCIdx;
|
||||||
}
|
}
|
||||||
// Create classes for InstRW defs.
|
// Create classes for InstRW defs.
|
||||||
|
@ -716,11 +713,11 @@ unsigned CodeGenSchedModels::addSchedClass(Record *ItinClassDef,
|
||||||
return Idx;
|
return Idx;
|
||||||
}
|
}
|
||||||
Idx = SchedClasses.size();
|
Idx = SchedClasses.size();
|
||||||
SchedClasses.resize(Idx+1);
|
SchedClasses.emplace_back(Idx,
|
||||||
|
createSchedClassName(ItinClassDef, OperWrites,
|
||||||
|
OperReads),
|
||||||
|
ItinClassDef);
|
||||||
CodeGenSchedClass &SC = SchedClasses.back();
|
CodeGenSchedClass &SC = SchedClasses.back();
|
||||||
SC.Index = Idx;
|
|
||||||
SC.Name = createSchedClassName(ItinClassDef, OperWrites, OperReads);
|
|
||||||
SC.ItinClassDef = ItinClassDef;
|
|
||||||
SC.Writes = OperWrites;
|
SC.Writes = OperWrites;
|
||||||
SC.Reads = OperReads;
|
SC.Reads = OperReads;
|
||||||
SC.ProcIndices = ProcIndices;
|
SC.ProcIndices = ProcIndices;
|
||||||
|
@ -788,10 +785,8 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
unsigned SCIdx = SchedClasses.size();
|
unsigned SCIdx = SchedClasses.size();
|
||||||
SchedClasses.resize(SCIdx+1);
|
SchedClasses.emplace_back(SCIdx, createSchedClassName(InstDefs), nullptr);
|
||||||
CodeGenSchedClass &SC = SchedClasses.back();
|
CodeGenSchedClass &SC = SchedClasses.back();
|
||||||
SC.Index = SCIdx;
|
|
||||||
SC.Name = createSchedClassName(InstDefs);
|
|
||||||
DEBUG(dbgs() << "InstRW: New SC " << SCIdx << ":" << SC.Name << " on "
|
DEBUG(dbgs() << "InstRW: New SC " << SCIdx << ":" << SC.Name << " on "
|
||||||
<< InstRWDef->getValueAsDef("SchedModel")->getName() << "\n");
|
<< InstRWDef->getValueAsDef("SchedModel")->getName() << "\n");
|
||||||
|
|
||||||
|
|
|
@ -139,7 +139,8 @@ struct CodeGenSchedClass {
|
||||||
// off to join another inferred class.
|
// off to join another inferred class.
|
||||||
RecVec InstRWs;
|
RecVec InstRWs;
|
||||||
|
|
||||||
CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {}
|
CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
|
||||||
|
: Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
|
||||||
|
|
||||||
bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
|
bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
|
||||||
ArrayRef<unsigned> R) const {
|
ArrayRef<unsigned> R) const {
|
||||||
|
@ -198,9 +199,9 @@ struct CodeGenProcModel {
|
||||||
// Per-operand machine model resources associated with this processor.
|
// Per-operand machine model resources associated with this processor.
|
||||||
RecVec ProcResourceDefs;
|
RecVec ProcResourceDefs;
|
||||||
|
|
||||||
CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
|
CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
|
||||||
Record *IDef) :
|
Record *IDef) :
|
||||||
Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
|
Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef) {}
|
||||||
|
|
||||||
bool hasItineraries() const {
|
bool hasItineraries() const {
|
||||||
return !ItinsDef->getValueAsListOfDefs("IID").empty();
|
return !ItinsDef->getValueAsListOfDefs("IID").empty();
|
||||||
|
|
Loading…
Reference in New Issue