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[Hexagon] Regenerate build-vector-v4i8-zext.ll to show full codegen

This commit is contained in:
Simon Pilgrim 2022-06-08 11:41:54 +01:00
parent b3c0918fb4
commit 27f970aac8
1 changed files with 15 additions and 1 deletions
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16
llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll
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@ -1,10 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we generate zero-extends, instead of just shifting and oring ; Check that we generate zero-extends, instead of just shifting and oring
; registers (which can contain sign-extended negative values). ; registers (which can contain sign-extended negative values).
; CHECK: and(r{{[0-9]+}},#255)
define i32 @fred(i8 %a0, i8 %a1, i8 %a2, i8 %a3) #0 { define i32 @fred(i8 %a0, i8 %a1, i8 %a2, i8 %a3) #0 {
; CHECK-LABEL: fred:
; CHECK: // %bb.0: // %b4
; CHECK-NEXT: {
; CHECK-NEXT: r1 = and(r1,#255)
; CHECK-NEXT: r3 = and(r3,#255)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = insert(r1,#24,#8)
; CHECK-NEXT: r2 = insert(r3,#24,#8)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = combine(r2.l,r0.l)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
b4: b4:
%v5 = insertelement <4 x i8> undef, i8 %a0, i32 0 %v5 = insertelement <4 x i8> undef, i8 %a0, i32 0
%v6 = insertelement <4 x i8> %v5, i8 %a1, i32 1 %v6 = insertelement <4 x i8> %v5, i8 %a1, i32 1