forked from OSchip/llvm-project
Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel."
This reverts commitc3492a1aa1. I think this is the wrong strategy and wrong place to do this transform anyway. Also reverts follow up commit7d593d0d69.
This commit is contained in:
Matt Arsenault
parent
455ca0ebb6
commit
27df165270
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@ -1244,11 +1244,6 @@ void SIFoldOperands::foldInstOperand(MachineInstr &MI,
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foldOperand(OpToFold, UseMI, OpNo, FoldList,
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CopiesToReplace);
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} else {
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// Skip updating literal use if it's used in the same REQ_SQUENCE as,
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// if that literal could be inlined, it's just a single use.
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if (NonInlineUse && NonInlineUse->getParent() == UseMI &&
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UseMI->isRegSequence())
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continue;
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if (++NumLiteralUses == 1) {
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NonInlineUse = &*Use;
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NonInlineUseOpNo = OpNo;
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@ -102,10 +102,6 @@ static cl::opt<bool> UseDivergentRegisterIndexing(
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cl::desc("Use indirect register addressing for divergent indexes"),
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cl::init(false));
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static cl::opt<bool> EnableLowerSGPRToVGPRCopy(
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"lower-sgpr-to-vgpr-copy", cl::Hidden,
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cl::desc("Enable lowering copy from SGPR to VGPR"), cl::init(true));
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static bool hasFP32Denormals(const MachineFunction &MF) {
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const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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return Info->getMode().allFP32Denormals();
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@ -11484,60 +11480,6 @@ bool SITargetLowering::checkAsmConstraintValA(SDValue Op,
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return false;
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}
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// Lower COPY from SGPR to VGPR to real one as they are real transfer instead
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// of COPY.
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static void lowerSGPRToVGPRCopy(MachineFunction &MF, MachineRegisterInfo &MRI,
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const SIRegisterInfo &TRI,
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const SIInstrInfo &TII) {
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for (MachineBasicBlock &MBB : MF) {
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for (auto BI = MBB.begin(), BE = MBB.end(); BI != BE; /*EMPTY*/) {
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MachineInstr &MI = *BI++;
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auto IsSGPRToVGPRCopy = [&MRI, &TRI](const MachineInstr &MI) {
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if (!MI.isCopy())
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return false;
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auto DstReg = MI.getOperand(0).getReg();
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auto SrcReg = MI.getOperand(1).getReg();
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const auto *DstRC = DstReg.isVirtual() ? MRI.getRegClass(DstReg)
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: TRI.getPhysRegClass(DstReg);
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const auto *SrcRC = SrcReg.isVirtual() ? MRI.getRegClass(SrcReg)
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: TRI.getPhysRegClass(SrcReg);
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return (DstRC == &AMDGPU::VGPR_32RegClass ||
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DstRC == &AMDGPU::VReg_64RegClass) &&
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(SrcRC == &AMDGPU::SGPR_32RegClass ||
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SrcRC == &AMDGPU::SGPR_64RegClass);
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};
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// Skip if it's not a copy from SGPR to VGPR.
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if (!IsSGPRToVGPRCopy(MI))
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continue;
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const MachineOperand &Src = MI.getOperand(1);
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// FIXME: Need subreg support.
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if (Src.getSubReg() != AMDGPU::NoSubRegister)
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continue;
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// FIXME: Need undef support.
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if (Src.getReg().isVirtual()) {
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auto *DefMI = MRI.getVRegDef(Src.getReg());
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if (!DefMI || DefMI->isImplicitDef())
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continue;
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}
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LLVM_DEBUG(dbgs() << "Lower COPY: " << MI);
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unsigned Opcode = (TRI.getRegSizeInBits(Src.getReg(), MRI) == 64)
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? AMDGPU::V_MOV_B64_PSEUDO
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: AMDGPU::V_MOV_B32_e32;
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auto DstReg = MI.getOperand(0).getReg();
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auto MIB = BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(Opcode), DstReg)
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.add(MI.getOperand(1));
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(void)MIB;
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LLVM_DEBUG(dbgs() << " to: " << *MIB.getInstr());
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MI.eraseFromParent();
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}
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}
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}
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// Figure out which registers should be reserved for stack access. Only after
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// the function is legalized do we know all of the non-spill stack objects or if
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// calls are present.
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@ -11546,10 +11488,6 @@ void SITargetLowering::finalizeLowering(MachineFunction &MF) const {
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SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
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const SIInstrInfo *TII = Subtarget->getInstrInfo();
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if (EnableLowerSGPRToVGPRCopy)
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lowerSGPRToVGPRCopy(MF, MRI, *TRI, *TII);
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if (Info->isEntryFunction()) {
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// Callable functions have fixed registers used for stack access.
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@ -11,7 +11,7 @@
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; SI: s_bitset0_b32 s{{[0-9]+}}, 31
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
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; VI: s_bitset0_b32 s{{[0-9]+}}, 31
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define amdgpu_kernel void @s_fabs_fn_free(float addrspace(1)* %out, i32 %in) {
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%bc= bitcast i32 %in to float
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@ -24,7 +24,7 @@ define amdgpu_kernel void @s_fabs_fn_free(float addrspace(1)* %out, i32 %in) {
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; SI: s_bitset0_b32 s{{[0-9]+}}, 31
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
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; VI: s_bitset0_b32 s{{[0-9]+}}, 31
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define amdgpu_kernel void @s_fabs_free(float addrspace(1)* %out, i32 %in) {
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%bc= bitcast i32 %in to float
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@ -36,7 +36,7 @@ define amdgpu_kernel void @s_fabs_free(float addrspace(1)* %out, i32 %in) {
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; FUNC-LABEL: {{^}}s_fabs_f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; SI: s_bitset0_b32 s{{[0-9]+}}, 31
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
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; VI: s_bitset0_b32 s{{[0-9]+}}, 31
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define amdgpu_kernel void @s_fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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@ -34,7 +34,7 @@ define amdgpu_kernel void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: s_bitset1_b32 s{{[0-9]+}}, 31
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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; VI: s_bitset1_b32 s{{[0-9]+}}, 31
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define amdgpu_kernel void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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@ -49,7 +49,7 @@ define amdgpu_kernel void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in)
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: s_bitset1_b32 s{{[0-9]+}}, 31
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define amdgpu_kernel void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @fabs(float %bc)
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@ -59,7 +59,7 @@ define amdgpu_kernel void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %
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}
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; FUNC-LABEL: {{^}}fneg_fabs_f32:
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; SI: s_bitset1_b32 s{{[0-9]+}}, 31
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define amdgpu_kernel void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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%fsub = fsub float -0.000000e+00, %fabs
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@ -1,26 +0,0 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -o - %s | FileCheck %s
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
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target triple = "amdgcn-amd-amdhsa"
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; CHECK-LABEL: {{^}}t0:
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; CHECK: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], s[4:5], 0x0
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; CHECK-COUNT-1: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]]
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; CHECK-NOT: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]]
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define protected amdgpu_kernel void @t0(float addrspace(1)* %p, i32 %i0, i32 %j0, i32 %k0) {
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entry:
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%0 = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i = add i32 %0, %i0
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%j = add i32 %0, %j0
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%k = add i32 %0, %k0
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%pi = getelementptr float, float addrspace(1)* %p, i32 %i
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%vi = load float, float addrspace(1)* %pi
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%pj = getelementptr float, float addrspace(1)* %p, i32 %j
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%vj = load float, float addrspace(1)* %pj
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%sum = fadd float %vi, %vj
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%pk = getelementptr float, float addrspace(1)* %p, i32 %k
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store float %sum, float addrspace(1)* %pk
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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@ -153,9 +153,7 @@ bb:
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; GCN-LABEL: barrier_vmcnt_vscnt_flat_workgroup:
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; GCN: flat_load_dword
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; GFX8_9: s_waitcnt lgkmcnt(0){{$}}
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; GFX8_9: s_waitcnt vmcnt(0){{$}}
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; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
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; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
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; GFX10: s_waitcnt_vscnt null, 0x0
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; GCN-NEXT: s_barrier
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define amdgpu_kernel void @barrier_vmcnt_vscnt_flat_workgroup(i32* %arg) {
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@ -650,12 +650,12 @@ main_body:
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; CHECK: image_store
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; CHECK: s_wqm_b64 exec, exec
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; CHECK-DAG: v_mov_b32_e32 [[CTR:v[0-9]+]], 0
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; CHECK-DAG: v_mov_b32_e32 [[SEVEN:v[0-9]+]], 0x40e00000
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; CHECK-DAG: s_mov_b32 [[SEVEN:s[0-9]+]], 0x40e00000
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; CHECK: [[LOOPHDR:BB[0-9]+_[0-9]+]]: ; %body
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; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]]
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; CHECK: [[LOOP:BB[0-9]+_[0-9]+]]: ; %loop
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; CHECK: v_cmp_gt_f32_e32 vcc, [[CTR]], [[SEVEN]]
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; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]]
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; CHECK: s_cbranch_vccz [[LOOPHDR]]
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; CHECK: ; %break
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