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Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0. 

llvm-svn: 57692
This commit is contained in:
Evan Cheng 2008-10-17 17:14:20 +00:00
parent 9e23d746bf
commit 27c3702267
2 changed files with 17 additions and 5 deletions
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18
llvm/lib/Target/X86/X86CodeEmitter.cpp
View File

@ -84,6 +84,7 @@ namespace {
intptr_t PCAdj = 0);
void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
void emitRegModRMByte(unsigned RegOpcodeField);
void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
void emitConstant(uint64_t Val, unsigned Size);
@ -231,6 +232,10 @@ void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
}
void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) {
MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
}
void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
// SIB byte is in the same format as the ModRMByte...
MCE.emitByte(ModRMByte(SS, Index, Base));
@ -631,10 +636,16 @@ void Emitter::emitInstruction(const MachineInstr &MI,
case X86II::MRM0r: case X86II::MRM1r:
case X86II::MRM2r: case X86II::MRM3r:
case X86II::MRM4r: case X86II::MRM5r:
case X86II::MRM6r: case X86II::MRM7r:
case X86II::MRM6r: case X86II::MRM7r: {
MCE.emitByte(BaseOpcode);
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
// Special handling of lfence and mfence.
if (Desc->getOpcode() == X86::LFENCE ||
Desc->getOpcode() == X86::MFENCE)
emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
else
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
@ -660,6 +671,7 @@ void Emitter::emitInstruction(const MachineInstr &MI,
}
}
break;
}
case X86II::MRM0m: case X86II::MRM1m:
case X86II::MRM2m: case X86II::MRM3m:

4
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -2239,9 +2239,9 @@ def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
TB, Requires<[HasSSE2]>;
// Load, store, and memory fence
def LFENCE : I<0xAE, MRM5m, (outs), (ins),
def LFENCE : I<0xAE, MRM5r, (outs), (ins),
"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
def MFENCE : I<0xAE, MRM6m, (outs), (ins),
def MFENCE : I<0xAE, MRM6r, (outs), (ins),
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
//TODO: custom lower this so as to never even generate the noop