forked from OSchip/llvm-project
AArch64Subtarget: Use default member initializers
llvm-svn: 271057
This commit is contained in:
parent
74b1fb00f7
commit
27b6692fe2
|
@ -50,12 +50,8 @@ AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
|
|||
AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
|
||||
const std::string &FS,
|
||||
const TargetMachine &TM, bool LittleEndian)
|
||||
: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
|
||||
HasV8_1aOps(false), HasV8_2aOps(false), HasFPARMv8(false), HasNEON(false),
|
||||
HasCrypto(false), HasCRC(false), HasPerfMon(false), HasFullFP16(false),
|
||||
HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
|
||||
StrictAlign(false), ReserveX18(TT.isOSDarwin()), IsLittle(LittleEndian),
|
||||
CPUString(CPU), TargetTriple(TT), FrameLowering(),
|
||||
: AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
|
||||
IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
|
||||
InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
|
||||
TLInfo(TM, *this), GISel() {}
|
||||
|
||||
|
|
|
@ -45,27 +45,27 @@ protected:
|
|||
};
|
||||
|
||||
/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
|
||||
ARMProcFamilyEnum ARMProcFamily;
|
||||
ARMProcFamilyEnum ARMProcFamily = Others;
|
||||
|
||||
bool HasV8_1aOps;
|
||||
bool HasV8_2aOps;
|
||||
bool HasV8_1aOps = false;
|
||||
bool HasV8_2aOps = false;
|
||||
|
||||
bool HasFPARMv8;
|
||||
bool HasNEON;
|
||||
bool HasCrypto;
|
||||
bool HasCRC;
|
||||
bool HasPerfMon;
|
||||
bool HasFullFP16;
|
||||
bool HasSPE;
|
||||
bool HasFPARMv8 = false;
|
||||
bool HasNEON = false;
|
||||
bool HasCrypto = false;
|
||||
bool HasCRC = false;
|
||||
bool HasPerfMon = false;
|
||||
bool HasFullFP16 = false;
|
||||
bool HasSPE = false;
|
||||
|
||||
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
|
||||
bool HasZeroCycleRegMove;
|
||||
bool HasZeroCycleRegMove = false;
|
||||
|
||||
// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
|
||||
bool HasZeroCycleZeroing;
|
||||
bool HasZeroCycleZeroing = false;
|
||||
|
||||
// StrictAlign - Disallow unaligned memory accesses.
|
||||
bool StrictAlign;
|
||||
bool StrictAlign = false;
|
||||
|
||||
// ReserveX18 - X18 is not available as a general purpose register.
|
||||
bool ReserveX18;
|
||||
|
|
Loading…
Reference in New Issue