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[ARM] Use post-RA MI scheduler when +use-misched is set 

Differential revision: https://reviews.llvm.org/D39100

llvm-svn: 316214
This commit is contained in:
Eugene Leviant 2017-10-20 14:29:17 +00:00
parent 46b791921f
commit 27b226fb65
2 changed files with 11 additions and 1 deletions
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9
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -310,7 +310,14 @@ namespace {
class ARMPassConfig : public TargetPassConfig {
public:
ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {}
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOpt::None) {
ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
TM.getTargetFeatureString());
if (STI.hasFeature(ARM::FeatureUseMISched))
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
}
}
ARMBaseTargetMachine &getARMTargetMachine() const {
return getTM<ARMBaseTargetMachine>();

3
llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll
View File

@ -1,5 +1,6 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED
; Check the latency for ALU shifted operand variants.
;
@ -60,6 +61,8 @@
; CHECK: Ready
; CHECK-NEXT: A57UnitI
; Check that post RA MI scheduler is invoked with +use-misched
; POST-MISCHED: Before post-MI-sched
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8r-arm-none-eabi"