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[SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI 

Summary:
Added a helper method in RegsForValue to get a list with
all the <RegNumber, RegSize> pairs that we want to iterate
over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and
in SelectionDAGBuilder::visitIntrinsicCall.

Reviewers: vsk

Reviewed By: vsk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46360

llvm-svn: 331510
This commit is contained in:
Bjorn Pettersson 2018-05-04 08:50:48 +00:00
parent 72fe760592
commit 27a841fe83
2 changed files with 43 additions and 40 deletions
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80
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -971,6 +971,20 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
}
}
SmallVector<std::pair<unsigned, unsigned>, 4>
RegsForValue::getRegsAndSizes() const {
SmallVector<std::pair<unsigned, unsigned>, 4> OutVec;
unsigned I = 0;
for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
unsigned RegCount = std::get<0>(CountAndVT);
MVT RegisterVT = std::get<1>(CountAndVT);
unsigned RegisterSize = RegisterVT.getSizeInBits();
for (unsigned E = I + RegCount; I != E; ++I)
OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
}
return OutVec;
}
void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
const TargetLibraryInfo *li) {
AA = aa;
@ -4908,26 +4922,18 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
const auto &TLI = DAG.getTargetLoweringInfo();
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
V->getType(), isABIRegCopy(V));
unsigned NumRegs =
std::accumulate(RFV.RegCount.begin(), RFV.RegCount.end(), 0);
if (NumRegs > 1) {
unsigned I = 0;
if (RFV.occupiesMultipleRegs()) {
unsigned Offset = 0;
auto RegisterVT = RFV.RegVTs.begin();
for (auto RegCount : RFV.RegCount) {
unsigned RegisterSize = (RegisterVT++)->getSizeInBits();
for (unsigned E = I + RegCount; I != E; ++I) {
// The vregs are guaranteed to be allocated in sequence.
Op = MachineOperand::CreateReg(VMI->second + I, false);
auto FragmentExpr = DIExpression::createFragmentExpression(
Expr, Offset, RegisterSize);
if (!FragmentExpr)
continue;
FuncInfo.ArgDbgValues.push_back(
BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
Op->getReg(), Variable, *FragmentExpr));
Offset += RegisterSize;
}
for (auto RegAndSize : RFV.getRegsAndSizes()) {
Op = MachineOperand::CreateReg(RegAndSize.first, false);
auto FragmentExpr = DIExpression::createFragmentExpression(
Expr, Offset, RegAndSize.second);
if (!FragmentExpr)
continue;
FuncInfo.ArgDbgValues.push_back(
BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
Op->getReg(), Variable, *FragmentExpr));
Offset += RegAndSize.second;
}
return true;
}
@ -5265,34 +5271,28 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
V->getType(), false);
if (RFV.occupiesMultipleRegs()) {
unsigned I = 0;
unsigned Offset = 0;
unsigned BitsToDescribe = 0;
if (auto VarSize = Variable->getSizeInBits())
BitsToDescribe = *VarSize;
if (auto Fragment = Expression->getFragmentInfo())
BitsToDescribe = Fragment->SizeInBits;
for (auto CountAndVT : zip_first(RFV.RegCount, RFV.RegVTs)) {
unsigned RegCount = std::get<0>(CountAndVT);
MVT RegisterVT = std::get<1>(CountAndVT);
unsigned RegisterSize = RegisterVT.getSizeInBits();
for (unsigned E = I + RegCount; I != E; ++I) {
// Bail out if all bits already are described.
if (Offset >= BitsToDescribe)
break;
unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
? BitsToDescribe - Offset
: RegisterSize;
auto FragmentExpr = DIExpression::createFragmentExpression(
Expression, Offset, FragmentSize);
if (!FragmentExpr)
for (auto RegAndSize : RFV.getRegsAndSizes()) {
unsigned RegisterSize = RegAndSize.second;
// Bail out if all bits are described already.
if (Offset >= BitsToDescribe)
break;
unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
? BitsToDescribe - Offset
: RegisterSize;
auto FragmentExpr = DIExpression::createFragmentExpression(
Expression, Offset, FragmentSize);
if (!FragmentExpr)
continue;
// The vregs are guaranteed to be allocated in sequence.
SDV = DAG.getVRegDbgValue(Variable, *FragmentExpr, Reg + I,
false, dl, SDNodeOrder);
DAG.AddDbgValue(SDV, nullptr, false);
Offset += RegisterSize;
}
SDV = DAG.getVRegDbgValue(Variable, *FragmentExpr, RegAndSize.first,
false, dl, SDNodeOrder);
DAG.AddDbgValue(SDV, nullptr, false);
Offset += RegisterSize;
}
} else {
SDV = DAG.getVRegDbgValue(Variable, Expression, Reg, false, dl,

3
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -1053,6 +1053,9 @@ struct RegsForValue {
bool occupiesMultipleRegs() const {
return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1;
}
/// Return a list of registers and their sizes.
SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const;
};
} // end namespace llvm