forked from OSchip/llvm-project
parent
357e8a390c
commit
27a546610c
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@ -1149,3 +1149,77 @@ define i64 @blsr64_branch(i64 %x) {
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}
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declare void @bar()
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define void @pr42118_i32(i32 %x) {
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; X86-LABEL: pr42118_i32:
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; X86: # %bb.0:
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; X86-NEXT: blsrl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: jne .LBB48_1
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; X86-NEXT: # %bb.2:
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; X86-NEXT: jmp bar # TAILCALL
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; X86-NEXT: .LBB48_1:
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; X86-NEXT: retl
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;
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; X64-LABEL: pr42118_i32:
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; X64: # %bb.0:
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; X64-NEXT: blsrl %edi, %eax
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; X64-NEXT: jne .LBB48_1
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; X64-NEXT: # %bb.2:
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; X64-NEXT: jmp bar # TAILCALL
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; X64-NEXT: .LBB48_1:
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; X64-NEXT: retq
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%tmp = sub i32 0, %x
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%tmp1 = and i32 %tmp, %x
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%cmp = icmp eq i32 %tmp1, %x
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br i1 %cmp, label %1, label %2
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tail call void @bar()
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br label %2
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ret void
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}
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define void @pr42118_i64(i64 %x) {
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; X86-LABEL: pr42118_i64:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .cfi_offset %esi, -8
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %eax, %edx
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; X86-NEXT: addl $-1, %edx
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; X86-NEXT: movl %ecx, %esi
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; X86-NEXT: adcl $-1, %esi
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; X86-NEXT: andl %eax, %edx
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; X86-NEXT: andl %ecx, %esi
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; X86-NEXT: orl %edx, %esi
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; X86-NEXT: jne .LBB49_1
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; X86-NEXT: # %bb.2:
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; X86-NEXT: popl %esi
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; X86-NEXT: .cfi_def_cfa_offset 4
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; X86-NEXT: jmp bar # TAILCALL
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; X86-NEXT: .LBB49_1:
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: popl %esi
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; X86-NEXT: .cfi_def_cfa_offset 4
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; X86-NEXT: retl
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;
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; X64-LABEL: pr42118_i64:
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; X64: # %bb.0:
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; X64-NEXT: blsrq %rdi, %rax
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; X64-NEXT: jne .LBB49_1
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; X64-NEXT: # %bb.2:
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; X64-NEXT: jmp bar # TAILCALL
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; X64-NEXT: .LBB49_1:
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; X64-NEXT: retq
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%tmp = sub i64 0, %x
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%tmp1 = and i64 %tmp, %x
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%cmp = icmp eq i64 %tmp1, %x
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br i1 %cmp, label %1, label %2
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tail call void @bar()
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br label %2
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ret void
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}
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