forked from OSchip/llvm-project
[TargetLowering] Extract simplifySetCCs ctpop into a separate function. NFCI
As requested in D89346. This allows us to add some early outs. I reordered some checks a little bit to make the more common bail outs happen earlier. Like checking opcode before checking hasOneUse. And I moved the bit width check to make sure it was safe to look through a truncate to the spot where we look through truncates instead of after. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D89494
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@ -3379,6 +3379,54 @@ SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
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return DAG.getSetCC(DL, VT, X, YShl1, Cond);
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}
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static SDValue simplifySetCCWithCTPOP(const TargetLowering &TLI, EVT VT,
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SDValue N0, const APInt &C1,
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ISD::CondCode Cond, const SDLoc &dl,
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SelectionDAG &DAG) {
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assert(!VT.isVector() && "Vectors are not supported yet!");
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// Look through truncs that don't change the value of a ctpop.
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SDValue CTPOP = N0;
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if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
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N0.getValueSizeInBits() > Log2_32(N0.getOperand(0).getValueSizeInBits()))
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CTPOP = N0.getOperand(0);
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if (CTPOP.getOpcode() != ISD::CTPOP || !CTPOP.hasOneUse())
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return SDValue();
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EVT CTVT = CTPOP.getValueType();
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SDValue CTOp = CTPOP.getOperand(0);
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// (ctpop x) u< 2 -> (x & x-1) == 0
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// (ctpop x) u> 1 -> (x & x-1) != 0
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if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)) {
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SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
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SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
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SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
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ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
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return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
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}
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// If ctpop is not supported, expand a power-of-2 comparison based on it.
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if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1 &&
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!TLI.isOperationLegalOrCustom(ISD::CTPOP, CTVT)) {
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// (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0)
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// (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
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SDValue Zero = DAG.getConstant(0, dl, CTVT);
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SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
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assert(CTVT.isInteger());
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ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, CTVT);
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SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
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SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
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SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond);
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SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond);
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unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
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return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS);
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}
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return SDValue();
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}
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/// Try to simplify a setcc built with the specified operands and cc. If it is
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/// unable to simplify it, return a null SDValue.
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SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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@ -3439,44 +3487,9 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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}
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}
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SDValue CTPOP = N0;
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// Look through truncs that don't change the value of a ctpop.
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if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
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CTPOP = N0.getOperand(0);
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if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
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(N0 == CTPOP ||
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N0.getValueSizeInBits() > Log2_32(CTPOP.getValueSizeInBits()))) {
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EVT CTVT = CTPOP.getValueType();
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SDValue CTOp = CTPOP.getOperand(0);
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// (ctpop x) u< 2 -> (x & x-1) == 0
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// (ctpop x) u> 1 -> (x & x-1) != 0
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if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
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SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
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SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
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SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
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ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
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return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
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}
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// If ctpop is not supported, expand a power-of-2 comparison based on it.
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if (C1 == 1 && !isOperationLegalOrCustom(ISD::CTPOP, CTVT) &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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// (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0)
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// (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
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SDValue Zero = DAG.getConstant(0, dl, CTVT);
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SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
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assert(CTVT.isInteger());
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ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, CTVT);
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SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
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SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
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SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond);
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SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond);
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unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
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return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS);
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}
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}
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// Optimize some CTPOP cases.
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if (SDValue V = simplifySetCCWithCTPOP(*this, VT, N0, C1, Cond, dl, DAG))
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return V;
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// (zext x) == C --> x == (trunc C)
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// (sext x) == C --> x == (trunc C)
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