forked from OSchip/llvm-project
[LLDB][MIPS] Emulation of MIPS64 floating-point branch instructions
Patch by Jaydeep Patil SUMMARY: 1. Added emulation of MIPS64 floating-point branch instructions 2. Updated GetRegisterInfo to recognize floating-point registers 3. Provided CPU information while creating createMCSubtargetInfo in disassembler 4. Bug fix in emulation of JIC and JIALC 5. Correct identification of breakpoint when set in a delay slot of a branch instruction Reviewers: clayborg Subscribers: bhushan, mohit.bhakkad, sagar, nitesh.jain, lldb-commits. Differential Revision: http://reviews.llvm.org/D10355 llvm-svn: 239996
This commit is contained in:
Mohit K. Bhakkad
parent
58ef391f3e
commit
276a930eda
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@ -415,7 +415,7 @@ protected:
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DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, unsigned flavor, DisassemblerLLVMC &owner):
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DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner):
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m_is_valid(true)
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{
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std::string Error;
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@ -431,7 +431,7 @@ DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, uns
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std::string features_str;
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m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, "",
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m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, cpu,
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features_str));
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std::unique_ptr<llvm::MCRegisterInfo> reg_info(curr_target->createMCRegInfo(triple));
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@ -637,7 +637,45 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s
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triple = thumb_arch.GetTriple().getTriple().c_str();
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}
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m_disasm_ap.reset (new LLVMCDisassembler(triple, flavor, *this));
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const char *cpu = "";
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switch (arch.GetCore())
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{
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case ArchSpec::eCore_mips32:
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case ArchSpec::eCore_mips32el:
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cpu = "mips32"; break;
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case ArchSpec::eCore_mips32r2:
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case ArchSpec::eCore_mips32r2el:
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cpu = "mips32r2"; break;
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case ArchSpec::eCore_mips32r3:
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case ArchSpec::eCore_mips32r3el:
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cpu = "mips32r3"; break;
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case ArchSpec::eCore_mips32r5:
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case ArchSpec::eCore_mips32r5el:
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cpu = "mips32r5"; break;
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case ArchSpec::eCore_mips32r6:
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case ArchSpec::eCore_mips32r6el:
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cpu = "mips32r6"; break;
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case ArchSpec::eCore_mips64:
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case ArchSpec::eCore_mips64el:
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cpu = "mips64"; break;
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case ArchSpec::eCore_mips64r2:
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case ArchSpec::eCore_mips64r2el:
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cpu = "mips64r2"; break;
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case ArchSpec::eCore_mips64r3:
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case ArchSpec::eCore_mips64r3el:
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cpu = "mips64r3"; break;
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case ArchSpec::eCore_mips64r5:
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case ArchSpec::eCore_mips64r5el:
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cpu = "mips64r5"; break;
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case ArchSpec::eCore_mips64r6:
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case ArchSpec::eCore_mips64r6el:
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cpu = "mips64r6"; break;
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default:
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cpu = ""; break;
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}
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m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, flavor, *this));
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if (!m_disasm_ap->IsValid())
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{
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// We use m_disasm_ap.get() to tell whether we are valid or not, so if this isn't good for some reason,
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@ -649,7 +687,7 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s
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if (arch.GetTriple().getArch() == llvm::Triple::arm)
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{
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std::string thumb_triple(thumb_arch.GetTriple().getTriple());
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m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), flavor, *this));
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m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), nullptr, flavor, *this));
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if (!m_alternate_disasm_ap->IsValid())
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{
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m_disasm_ap.reset();
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@ -41,7 +41,7 @@ class DisassemblerLLVMC : public lldb_private::Disassembler
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class LLVMCDisassembler
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{
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public:
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LLVMCDisassembler (const char *triple, unsigned flavor, DisassemblerLLVMC &owner);
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LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner);
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~LLVMCDisassembler();
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@ -211,6 +211,38 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name
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case gcc_dwarf_sp_mips64: return "r29";
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case gcc_dwarf_r30_mips64: return "r30";
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case gcc_dwarf_ra_mips64: return "r31";
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case gcc_dwarf_f0_mips64: return "f0";
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case gcc_dwarf_f1_mips64: return "f1";
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case gcc_dwarf_f2_mips64: return "f2";
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case gcc_dwarf_f3_mips64: return "f3";
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case gcc_dwarf_f4_mips64: return "f4";
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case gcc_dwarf_f5_mips64: return "f5";
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case gcc_dwarf_f6_mips64: return "f6";
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case gcc_dwarf_f7_mips64: return "f7";
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case gcc_dwarf_f8_mips64: return "f8";
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case gcc_dwarf_f9_mips64: return "f9";
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case gcc_dwarf_f10_mips64: return "f10";
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case gcc_dwarf_f11_mips64: return "f11";
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case gcc_dwarf_f12_mips64: return "f12";
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case gcc_dwarf_f13_mips64: return "f13";
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case gcc_dwarf_f14_mips64: return "f14";
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case gcc_dwarf_f15_mips64: return "f15";
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case gcc_dwarf_f16_mips64: return "f16";
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case gcc_dwarf_f17_mips64: return "f17";
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case gcc_dwarf_f18_mips64: return "f18";
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case gcc_dwarf_f19_mips64: return "f19";
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case gcc_dwarf_f20_mips64: return "f20";
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case gcc_dwarf_f21_mips64: return "f21";
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case gcc_dwarf_f22_mips64: return "f22";
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case gcc_dwarf_f23_mips64: return "f23";
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case gcc_dwarf_f24_mips64: return "f24";
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case gcc_dwarf_f25_mips64: return "f25";
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case gcc_dwarf_f26_mips64: return "f26";
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case gcc_dwarf_f27_mips64: return "f27";
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case gcc_dwarf_f28_mips64: return "f28";
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case gcc_dwarf_f29_mips64: return "f29";
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case gcc_dwarf_f30_mips64: return "f30";
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case gcc_dwarf_f31_mips64: return "f31";
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default:
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break;
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}
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@ -257,7 +289,40 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name
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case gcc_dwarf_bad_mips64: return "bad";
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case gcc_dwarf_cause_mips64: return "cause";
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case gcc_dwarf_pc_mips64: return "pc";
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case gcc_dwarf_f0_mips64: return "fp_reg[0]";
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case gcc_dwarf_f1_mips64: return "fp_reg[1]";
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case gcc_dwarf_f2_mips64: return "fp_reg[2]";
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case gcc_dwarf_f3_mips64: return "fp_reg[3]";
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case gcc_dwarf_f4_mips64: return "fp_reg[4]";
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case gcc_dwarf_f5_mips64: return "fp_reg[5]";
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case gcc_dwarf_f6_mips64: return "fp_reg[6]";
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case gcc_dwarf_f7_mips64: return "fp_reg[7]";
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case gcc_dwarf_f8_mips64: return "fp_reg[8]";
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case gcc_dwarf_f9_mips64: return "fp_reg[9]";
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case gcc_dwarf_f10_mips64: return "fp_reg[10]";
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case gcc_dwarf_f11_mips64: return "fp_reg[11]";
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case gcc_dwarf_f12_mips64: return "fp_reg[12]";
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case gcc_dwarf_f13_mips64: return "fp_reg[13]";
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case gcc_dwarf_f14_mips64: return "fp_reg[14]";
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case gcc_dwarf_f15_mips64: return "fp_reg[15]";
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case gcc_dwarf_f16_mips64: return "fp_reg[16]";
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case gcc_dwarf_f17_mips64: return "fp_reg[17]";
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case gcc_dwarf_f18_mips64: return "fp_reg[18]";
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case gcc_dwarf_f19_mips64: return "fp_reg[19]";
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case gcc_dwarf_f20_mips64: return "fp_reg[20]";
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case gcc_dwarf_f21_mips64: return "fp_reg[21]";
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case gcc_dwarf_f22_mips64: return "fp_reg[22]";
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case gcc_dwarf_f23_mips64: return "fp_reg[23]";
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case gcc_dwarf_f24_mips64: return "fp_reg[24]";
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case gcc_dwarf_f25_mips64: return "fp_reg[25]";
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case gcc_dwarf_f26_mips64: return "fp_reg[26]";
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case gcc_dwarf_f27_mips64: return "fp_reg[27]";
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case gcc_dwarf_f28_mips64: return "fp_reg[28]";
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case gcc_dwarf_f29_mips64: return "fp_reg[29]";
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case gcc_dwarf_f30_mips64: return "fp_reg[30]";
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case gcc_dwarf_f31_mips64: return "fp_reg[31]";
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case gcc_dwarf_fcsr_mips64: return "fcsr";
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case gcc_dwarf_fir_mips64: return "fir";
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}
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return nullptr;
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}
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@ -284,13 +349,13 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n
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::memset (®_info, 0, sizeof(RegisterInfo));
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::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
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if (reg_num == gcc_dwarf_sr_mips64)
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if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64)
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{
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reg_info.byte_size = 4;
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reg_info.format = eFormatHex;
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reg_info.encoding = eEncodingUint;
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}
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else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_pc_mips64)
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else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_f31_mips64)
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{
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reg_info.byte_size = 8;
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reg_info.format = eFormatHex;
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@ -383,6 +448,16 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name)
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{ "JIC", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset" },
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{ "JR", &EmulateInstructionMIPS64::Emulate_JR, "JR target" },
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{ "JR_HB", &EmulateInstructionMIPS64::Emulate_JR, "JR.HB target" },
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{ "BC1F", &EmulateInstructionMIPS64::Emulate_BC1F, "BC1F cc, offset" },
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{ "BC1T", &EmulateInstructionMIPS64::Emulate_BC1T, "BC1T cc, offset" },
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{ "BC1FL", &EmulateInstructionMIPS64::Emulate_BC1FL, "BC1FL cc, offset" },
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{ "BC1TL", &EmulateInstructionMIPS64::Emulate_BC1TL, "BC1TL cc, offset" },
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{ "BC1EQZ", &EmulateInstructionMIPS64::Emulate_BC1EQZ, "BC1EQZ ft, offset" },
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{ "BC1NEZ", &EmulateInstructionMIPS64::Emulate_BC1NEZ, "BC1NEZ ft, offset" },
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{ "BC1ANY2F", &EmulateInstructionMIPS64::Emulate_BC1ANY2F, "BC1ANY2F cc, offset" },
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{ "BC1ANY2T", &EmulateInstructionMIPS64::Emulate_BC1ANY2T, "BC1ANY2T cc, offset" },
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{ "BC1ANY4F", &EmulateInstructionMIPS64::Emulate_BC1ANY4F, "BC1ANY4F cc, offset" },
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{ "BC1ANY4T", &EmulateInstructionMIPS64::Emulate_BC1ANY4T, "BC1ANY4T cc, offset" },
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};
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static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);
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@ -2347,7 +2422,7 @@ EmulateInstructionMIPS64::Emulate_JIALC (llvm::MCInst& insn)
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* RA = PC + 4
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*/
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rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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offset = insn.getOperand(0).getImm();
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offset = insn.getOperand(1).getImm();
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pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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@ -2383,7 +2458,7 @@ EmulateInstructionMIPS64::Emulate_JIC (llvm::MCInst& insn)
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* PC = GPR[rt] + offset
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*/
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rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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offset = insn.getOperand(0).getImm();
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offset = insn.getOperand(1).getImm();
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rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success);
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if (!success)
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@ -2423,3 +2498,420 @@ EmulateInstructionMIPS64::Emulate_JR (llvm::MCInst& insn)
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn)
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{
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bool success = false;
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uint32_t cc, fcsr;
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int64_t target, pc, offset;
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/*
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* BC1F cc, offset
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* condition <- (FPConditionCode(cc) == 0)
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* if condition then
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* offset = sign_ext (offset)
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* PC = PC + offset
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*/
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cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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offset = insn.getOperand(1).getImm();
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pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
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if (!success)
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return false;
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/* fcsr[23], fcsr[25-31] are vaild condition bits */
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fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
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if ((fcsr & (1 << cc)) == 0)
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target = pc + offset;
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else
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target = pc + 4;
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Context context;
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
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return false;
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn)
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{
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bool success = false;
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uint32_t cc, fcsr;
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int64_t target, pc, offset;
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/*
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* BC1T cc, offset
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* condition <- (FPConditionCode(cc) != 0)
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* if condition then
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* offset = sign_ext (offset)
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* PC = PC + offset
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*/
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cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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offset = insn.getOperand(1).getImm();
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pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
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if (!success)
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return false;
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/* fcsr[23], fcsr[25-31] are vaild condition bits */
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fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
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if ((fcsr & (1 << cc)) != 0)
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target = pc + offset;
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else
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target = pc + 4;
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Context context;
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
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return false;
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn)
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{
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bool success = false;
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uint32_t cc, fcsr;
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int64_t target, pc, offset;
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/*
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* BC1F cc, offset
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* condition <- (FPConditionCode(cc) == 0)
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* if condition then
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* offset = sign_ext (offset)
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* PC = PC + offset
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*/
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cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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offset = insn.getOperand(1).getImm();
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pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
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if (!success)
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return false;
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/* fcsr[23], fcsr[25-31] are vaild condition bits */
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fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
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if ((fcsr & (1 << cc)) == 0)
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target = pc + offset;
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else
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target = pc + 8; /* skip delay slot */
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Context context;
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
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return false;
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn)
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{
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bool success = false;
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uint32_t cc, fcsr;
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int64_t target, pc, offset;
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/*
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* BC1T cc, offset
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* condition <- (FPConditionCode(cc) != 0)
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* if condition then
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* offset = sign_ext (offset)
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* PC = PC + offset
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*/
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cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
|
||||
offset = insn.getOperand(1).getImm();
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
/* fcsr[23], fcsr[25-31] are vaild condition bits */
|
||||
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
|
||||
|
||||
if ((fcsr & (1 << cc)) != 0)
|
||||
target = pc + offset;
|
||||
else
|
||||
target = pc + 8; /* skip delay slot */
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_BC1EQZ (llvm::MCInst& insn)
|
||||
{
|
||||
bool success = false;
|
||||
uint32_t ft;
|
||||
uint64_t ft_val;
|
||||
int64_t target, pc, offset;
|
||||
|
||||
/*
|
||||
* BC1EQZ ft, offset
|
||||
* condition <- (FPR[ft].bit0 == 0)
|
||||
* if condition then
|
||||
* offset = sign_ext (offset)
|
||||
* PC = PC + 4 + offset
|
||||
*/
|
||||
ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
|
||||
offset = insn.getOperand(1).getImm();
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
if ((ft_val & 1) == 0)
|
||||
target = pc + 4 + offset;
|
||||
else
|
||||
target = pc + 4;
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn)
|
||||
{
|
||||
bool success = false;
|
||||
uint32_t ft;
|
||||
uint64_t ft_val;
|
||||
int64_t target, pc, offset;
|
||||
|
||||
/*
|
||||
* BC1NEZ ft, offset
|
||||
* condition <- (FPR[ft].bit0 != 0)
|
||||
* if condition then
|
||||
* offset = sign_ext (offset)
|
||||
* PC = PC + 4 + offset
|
||||
*/
|
||||
ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
|
||||
offset = insn.getOperand(1).getImm();
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
if ((ft_val & 1) != 0)
|
||||
target = pc + 4 + offset;
|
||||
else
|
||||
target = pc + 4;
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn)
|
||||
{
|
||||
bool success = false;
|
||||
uint32_t cc, fcsr;
|
||||
int64_t target, pc, offset;
|
||||
|
||||
/*
|
||||
* BC1ANY2F cc, offset
|
||||
* condition <- (FPConditionCode(cc) == 0
|
||||
* || FPConditionCode(cc+1) == 0)
|
||||
* if condition then
|
||||
* offset = sign_ext (offset)
|
||||
* PC = PC + offset
|
||||
*/
|
||||
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
|
||||
offset = insn.getOperand(1).getImm();
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
/* fcsr[23], fcsr[25-31] are vaild condition bits */
|
||||
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
|
||||
|
||||
/* if any one bit is 0 */
|
||||
if (((fcsr >> cc) & 3) != 3)
|
||||
target = pc + offset;
|
||||
else
|
||||
target = pc + 4;
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn)
|
||||
{
|
||||
bool success = false;
|
||||
uint32_t cc, fcsr;
|
||||
int64_t target, pc, offset;
|
||||
|
||||
/*
|
||||
* BC1ANY2T cc, offset
|
||||
* condition <- (FPConditionCode(cc) == 1
|
||||
* || FPConditionCode(cc+1) == 1)
|
||||
* if condition then
|
||||
* offset = sign_ext (offset)
|
||||
* PC = PC + offset
|
||||
*/
|
||||
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
|
||||
offset = insn.getOperand(1).getImm();
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
/* fcsr[23], fcsr[25-31] are vaild condition bits */
|
||||
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
|
||||
|
||||
/* if any one bit is 1 */
|
||||
if (((fcsr >> cc) & 3) != 0)
|
||||
target = pc + offset;
|
||||
else
|
||||
target = pc + 4;
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn)
|
||||
{
|
||||
bool success = false;
|
||||
uint32_t cc, fcsr;
|
||||
int64_t target, pc, offset;
|
||||
|
||||
/*
|
||||
* BC1ANY4F cc, offset
|
||||
* condition <- (FPConditionCode(cc) == 0
|
||||
* || FPConditionCode(cc+1) == 0)
|
||||
* || FPConditionCode(cc+2) == 0)
|
||||
* || FPConditionCode(cc+3) == 0)
|
||||
* if condition then
|
||||
* offset = sign_ext (offset)
|
||||
* PC = PC + offset
|
||||
*/
|
||||
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
|
||||
offset = insn.getOperand(1).getImm();
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
/* fcsr[23], fcsr[25-31] are vaild condition bits */
|
||||
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
|
||||
|
||||
/* if any one bit is 0 */
|
||||
if (((fcsr >> cc) & 0xf) != 0xf)
|
||||
target = pc + offset;
|
||||
else
|
||||
target = pc + 4;
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn)
|
||||
{
|
||||
bool success = false;
|
||||
uint32_t cc, fcsr;
|
||||
int64_t target, pc, offset;
|
||||
|
||||
/*
|
||||
* BC1ANY4T cc, offset
|
||||
* condition <- (FPConditionCode(cc) == 1
|
||||
* || FPConditionCode(cc+1) == 1)
|
||||
* || FPConditionCode(cc+2) == 1)
|
||||
* || FPConditionCode(cc+3) == 1)
|
||||
* if condition then
|
||||
* offset = sign_ext (offset)
|
||||
* PC = PC + offset
|
||||
*/
|
||||
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
|
||||
offset = insn.getOperand(1).getImm();
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
/* fcsr[23], fcsr[25-31] are vaild condition bits */
|
||||
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
|
||||
|
||||
/* if any one bit is 1 */
|
||||
if (((fcsr >> cc) & 0xf) != 0)
|
||||
target = pc + offset;
|
||||
else
|
||||
target = pc + 4;
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -265,6 +265,36 @@ protected:
|
|||
bool
|
||||
Emulate_JR (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1F (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1T (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1FL (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1TL (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1EQZ (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1NEZ (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1ANY2F (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1ANY2T (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1ANY4F (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BC1ANY4T (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
nonvolatile_reg_p (uint64_t regnum);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue