From 27351f2022c56b830f91d7f526775693fd9043e9 Mon Sep 17 00:00:00 2001 From: Saleem Abdulrasool Date: Wed, 14 May 2014 03:47:39 +0000 Subject: [PATCH] ARM: implement support for the UDF mnemonic The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751 --- llvm/lib/Target/ARM/ARMInstrInfo.td | 12 ++++++ llvm/lib/Target/ARM/ARMInstrThumb.td | 9 +++++ llvm/lib/Target/ARM/ARMInstrThumb2.td | 13 +++++++ .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 5 ++- llvm/test/MC/ARM/udf-arm-diagnostics.s | 19 +++++++++ llvm/test/MC/ARM/udf-arm.s | 11 ++++++ llvm/test/MC/ARM/udf-thumb-2-diagnostics.s | 25 ++++++++++++ llvm/test/MC/ARM/udf-thumb-2.s | 13 +++++++ llvm/test/MC/ARM/udf-thumb-diagnostics.s | 19 +++++++++ llvm/test/MC/ARM/udf-thumb.s | 11 ++++++ .../MC/Disassembler/ARM/invalid-thumbv7.txt | 39 ------------------- 11 files changed, 135 insertions(+), 41 deletions(-) create mode 100644 llvm/test/MC/ARM/udf-arm-diagnostics.s create mode 100644 llvm/test/MC/ARM/udf-arm.s create mode 100644 llvm/test/MC/ARM/udf-thumb-2-diagnostics.s create mode 100644 llvm/test/MC/ARM/udf-thumb-2.s create mode 100644 llvm/test/MC/ARM/udf-thumb-diagnostics.s create mode 100644 llvm/test/MC/ARM/udf-thumb.s diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 1d2a7e1be43d..d449730e9993 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1967,6 +1967,18 @@ def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", let Inst{3-0} = opt; } +// A8.8.247 UDF - Undefined (Encoding A1) +def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, + "udf", "\t$imm16", []> { + bits<16> imm16; + let Inst{31-28} = 0b1110; // AL + let Inst{27-25} = 0b011; + let Inst{24-20} = 0b11111; + let Inst{19-8} = imm16{15-4}; + let Inst{7-4} = 0b1111; + let Inst{3-0} = imm16{3-0}; +} + /* * A5.4 Permanently UNDEFINED instructions. * diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 170c2ffab54d..ff3832d98b5e 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -1193,6 +1193,15 @@ def tTST : // A8.6.230 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, Sched<[WriteALU]>; +// A8.8.247 UDF - Undefined (Encoding T1) +def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", []>, + Encoding16 { + bits<8> imm8; + let Inst{15-12} = 0b1101; + let Inst{11-8} = 0b1110; + let Inst{7-0} = imm8; +} + // Zero-extend byte def tUXTB : // A8.6.262 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 1e4aa0d6abec..28f528a510e9 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -2407,6 +2407,19 @@ def t2UBFX: T2TwoRegBitFI< let Inst{15} = 0; } +// A8.8.247 UDF - Undefined (Encoding T2) +def t2UDF + : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", []> { + bits<16> imm16; + let Inst{31-29} = 0b111; + let Inst{28-27} = 0b10; + let Inst{26-20} = 0b1111111; + let Inst{19-16} = imm16{15-12}; + let Inst{15} = 0b1; + let Inst{14-12} = 0b010; + let Inst{11-0} = imm16{11-0}; +} + // A8.6.18 BFI - Bitfield insert (Encoding T1) let Constraints = "$src = $Rd" in { def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd), diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 987f14d5dcb4..d24c83abe110 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5094,8 +5094,9 @@ getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || - Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") || - Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") || + Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" || + Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") || + Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" || diff --git a/llvm/test/MC/ARM/udf-arm-diagnostics.s b/llvm/test/MC/ARM/udf-arm-diagnostics.s new file mode 100644 index 000000000000..9ec9bf2124f0 --- /dev/null +++ b/llvm/test/MC/ARM/udf-arm-diagnostics.s @@ -0,0 +1,19 @@ +@ RUN: not llvm-mc -triple arm-eabi %s 2>&1 | FileCheck %s + + .syntax unified + .text + .arm + +undefined: + udfpl + +@ CHECK: error: instruction 'udf' is not predicable, but condition code specified +@ CHECK: udfpl +@ CHECK: ^ + + udf #65536 + +@ CHECK: error: invalid operand for instruction +@ CHECK: udf #65536 +@ CHECK: ^ + diff --git a/llvm/test/MC/ARM/udf-arm.s b/llvm/test/MC/ARM/udf-arm.s new file mode 100644 index 000000000000..a9d19ca66e6c --- /dev/null +++ b/llvm/test/MC/ARM/udf-arm.s @@ -0,0 +1,11 @@ +@ RUN: llvm-mc -triple arm-eabi -show-encoding %s | FileCheck %s + + .syntax unified + .text + .arm + +undefined: + udf #0 + +@ CHECK: udf #0 @ encoding: [0xf0,0x00,0xf0,0xe7] + diff --git a/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s b/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s new file mode 100644 index 000000000000..f8375601a031 --- /dev/null +++ b/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s @@ -0,0 +1,25 @@ +@ RUN: not llvm-mc -triple thumbv7-eabi -mattr +thumb2 %s 2>&1 | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udfpl + +@ CHECK: error: instruction 'udf' is not predicable, but condition code specified +@ CHECK: udfpl +@ CHECK: ^ + + udf #256 + +@ CHECK: error: instruction requires: arm-mode +@ CHECK: udf #256 +@ CHECK: ^ + + udf.w #65536 + +@ CHECK: error: invalid operand for instruction +@ CHECK: udf.w #65536 +@ CHECK: ^ + diff --git a/llvm/test/MC/ARM/udf-thumb-2.s b/llvm/test/MC/ARM/udf-thumb-2.s new file mode 100644 index 000000000000..beb6549cb08f --- /dev/null +++ b/llvm/test/MC/ARM/udf-thumb-2.s @@ -0,0 +1,13 @@ +@ RUN: llvm-mc -triple thumbv7-eabi -mattr +thumb2 -show-encoding %s | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udf #0 + udf.w #0 + +@ CHECK: udf #0 @ encoding: [0x00,0xde] +@ CHECK: udf.w #0 @ encoding: [0xf0,0xf7,0x00,0xa0] + diff --git a/llvm/test/MC/ARM/udf-thumb-diagnostics.s b/llvm/test/MC/ARM/udf-thumb-diagnostics.s new file mode 100644 index 000000000000..51388d0f10d6 --- /dev/null +++ b/llvm/test/MC/ARM/udf-thumb-diagnostics.s @@ -0,0 +1,19 @@ +@ RUN: not llvm-mc -triple thumbv6m-eabi %s 2>&1 | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udfpl + +@ CHECK: error: conditional execution not supported in Thumb1 +@ CHECK: udfpl +@ CHECK: ^ + + udf #256 + +@ CHECK: error: instruction requires: arm-mode +@ CHECK: udf #256 +@ CHECK: ^ + diff --git a/llvm/test/MC/ARM/udf-thumb.s b/llvm/test/MC/ARM/udf-thumb.s new file mode 100644 index 000000000000..10b3aff1aa30 --- /dev/null +++ b/llvm/test/MC/ARM/udf-thumb.s @@ -0,0 +1,11 @@ +@ RUN: llvm-mc -triple thumbv6m-eabi -show-encoding %s | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udf #0 + +@ CHECK: udf #0 @ encoding: [0x00,0xde] + diff --git a/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt index 2c84b8a7aa57..5257633e579f 100644 --- a/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt +++ b/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -21,17 +21,6 @@ # CHECK: warning: invalid instruction encoding # CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] -# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if cond = '1110' then UNDEFINED -[0x6f 0xde] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x6f 0xde] - #------------------------------------------------------------------------------ # Undefined encoding for it #------------------------------------------------------------------------------ @@ -248,34 +237,6 @@ # CHECK: warning: potentially undefined instruction encoding # CHECK-NEXT: [0xe4 0xe9 0x02 0x46] -#------------------------------------------------------------------------------ -# Undefined encodings for NEON/VFP instructions with invalid predicate bits -#------------------------------------------------------------------------------ - -# VABS -[0x40 0xde 0x00 0x0a] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x40 0xde 0x00 0x0a] - - -# VMLA -[0xf0 0xde 0xe0 0x0b] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b] - -# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) - -# VMOV -[0x00 0xde 0x10 0x0b] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x00 0xde 0x10 0x0b] - -# VDUP -[0xff 0xde 0xf0 0xfb] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0xff 0xde 0xf0 0xfb] - - #------------------------------------------------------------------------------ # Undefined encodings for NEON vld instructions #------------------------------------------------------------------------------