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[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions. 

The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior.

llvm-svn: 213750
This commit is contained in:
Tilmann Scheller 2014-07-23 13:03:47 +00:00
parent a4d18fc606
commit 2727279117
2 changed files with 21 additions and 1 deletions
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6
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5731,7 +5731,11 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
case ARM::STR_PRE_IMM:
case ARM::STR_PRE_REG:
case ARM::STR_POST_IMM:
case ARM::STR_POST_REG: {
case ARM::STR_POST_REG:
case ARM::STRB_PRE_IMM:
case ARM::STRB_PRE_REG:
case ARM::STRB_POST_IMM:
case ARM::STRB_POST_REG: {
// Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());

16
llvm/test/MC/ARM/diagnostics.s
View File

@ -496,6 +496,10 @@ foo2:
str r0, [r0, r1]!
str r0, [r0], #4
str r0, [r0], r1
strb r0, [r0, #1]!
strb r0, [r0, r1]!
strb r0, [r0], #1
strb r0, [r0], r1
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0, #4]!
@ CHECK-ERRORS: ^
@ -508,3 +512,15 @@ foo2:
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0, #1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0], #1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0], r1
@ CHECK-ERRORS: ^