forked from OSchip/llvm-project
AMDGPU: Consolidate inline immediate predicate functions
llvm-svn: 288718
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c0bd197c6b
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@ -666,6 +666,10 @@ public:
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return AMDGPU::isVI(getSTI());
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}
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bool hasInv2PiInlineImm() const {
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return getSTI().getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
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}
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bool hasSGPR102_SGPR103() const {
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return !isVI();
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}
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@ -855,7 +859,8 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const {
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if (Imm.IsFPImm) { // We got fp literal token
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if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
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return AMDGPU::isInlinableLiteral64(Imm.Val, AsmParser->isVI());
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return AMDGPU::isInlinableLiteral64(Imm.Val,
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AsmParser->hasInv2PiInlineImm());
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}
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APFloat FPLiteral(APFloat::IEEEdouble, APInt(64, Imm.Val));
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@ -865,18 +870,19 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const {
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// Check if single precision literal is inlinable
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return AMDGPU::isInlinableLiteral32(
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static_cast<int32_t>(FPLiteral.bitcastToAPInt().getZExtValue()),
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AsmParser->isVI());
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AsmParser->hasInv2PiInlineImm());
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}
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// We got int literal token.
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if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
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return AMDGPU::isInlinableLiteral64(Imm.Val, AsmParser->isVI());
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return AMDGPU::isInlinableLiteral64(Imm.Val,
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AsmParser->hasInv2PiInlineImm());
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}
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return AMDGPU::isInlinableLiteral32(
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static_cast<int32_t>(Literal.getLoBits(32).getZExtValue()),
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AsmParser->isVI());
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AsmParser->hasInv2PiInlineImm());
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}
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bool AMDGPUOperand::isLiteralImm(MVT type) const {
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@ -945,7 +951,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val) const {
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if (Imm.IsFPImm) { // We got fp literal token
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if (OpSize == 8) { // Expected 64-bit operand
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// Check if literal is inlinable
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if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), AsmParser->isVI())) {
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if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
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AsmParser->hasInv2PiInlineImm())) {
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Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
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} else if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand
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// For fp operands we check if low 32 bits are zeros
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@ -974,13 +981,15 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val) const {
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} else { // We got int literal token
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if (OpSize == 8) { // Expected 64-bit operand
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auto LiteralVal = Literal.getZExtValue();
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if (AMDGPU::isInlinableLiteral64(LiteralVal, AsmParser->isVI())) {
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if (AMDGPU::isInlinableLiteral64(LiteralVal,
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AsmParser->hasInv2PiInlineImm())) {
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Inst.addOperand(MCOperand::createImm(LiteralVal));
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return;
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}
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} else { // Expected 32-bit operand
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auto LiteralVal = static_cast<int32_t>(Literal.getLoBits(32).getZExtValue());
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if (AMDGPU::isInlinableLiteral32(LiteralVal, AsmParser->isVI())) {
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if (AMDGPU::isInlinableLiteral32(LiteralVal,
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AsmParser->hasInv2PiInlineImm())) {
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Inst.addOperand(MCOperand::createImm(LiteralVal));
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return;
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}
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@ -1673,44 +1673,16 @@ bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
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}
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bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
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int64_t SVal = Imm.getSExtValue();
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if (SVal >= -16 && SVal <= 64)
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return true;
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if (Imm.getBitWidth() == 64) {
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uint64_t Val = Imm.getZExtValue();
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return (DoubleToBits(0.0) == Val) ||
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(DoubleToBits(1.0) == Val) ||
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(DoubleToBits(-1.0) == Val) ||
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(DoubleToBits(0.5) == Val) ||
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(DoubleToBits(-0.5) == Val) ||
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(DoubleToBits(2.0) == Val) ||
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(DoubleToBits(-2.0) == Val) ||
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(DoubleToBits(4.0) == Val) ||
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(DoubleToBits(-4.0) == Val) ||
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(ST.hasInv2PiInlineImm() && Val == 0x3fc45f306dc9c882);
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switch (Imm.getBitWidth()) {
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case 32:
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return AMDGPU::isInlinableLiteral32(Imm.getSExtValue(),
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ST.hasInv2PiInlineImm());
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case 64:
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return AMDGPU::isInlinableLiteral64(Imm.getSExtValue(),
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ST.hasInv2PiInlineImm());
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default:
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llvm_unreachable("invalid bitwidth");
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}
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// The actual type of the operand does not seem to matter as long
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// as the bits match one of the inline immediate values. For example:
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//
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// -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
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// so it is a legal inline immediate.
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//
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// 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
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// floating-point, so it is a legal inline immediate.
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uint32_t Val = Imm.getZExtValue();
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return (FloatToBits(0.0f) == Val) ||
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(FloatToBits(1.0f) == Val) ||
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(FloatToBits(-1.0f) == Val) ||
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(FloatToBits(0.5f) == Val) ||
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(FloatToBits(-0.5f) == Val) ||
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(FloatToBits(2.0f) == Val) ||
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(FloatToBits(-2.0f) == Val) ||
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(FloatToBits(4.0f) == Val) ||
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(FloatToBits(-4.0f) == Val) ||
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(ST.hasInv2PiInlineImm() && Val == 0x3e22f983);
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}
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bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
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@ -1721,9 +1693,16 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
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// 32-bit floating point immediate bit pattern is legal for an integer
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// immediate. It would be for any 32-bit integer operand, but would not be
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// for a 64-bit one.
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unsigned BitSize = 8 * OpSize;
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return isInlineConstant(APInt(BitSize, MO.getImm(), true));
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switch (OpSize) {
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case 4:
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return AMDGPU::isInlinableLiteral32(static_cast<int32_t>(MO.getImm()),
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ST.hasInv2PiInlineImm());
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case 8:
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return AMDGPU::isInlinableLiteral64(MO.getImm(),
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ST.hasInv2PiInlineImm());
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default:
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llvm_unreachable("invalid bitwidth");
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}
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}
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return false;
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@ -392,40 +392,38 @@ unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
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return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
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}
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bool isInlinableLiteral64(int64_t Literal, bool IsVI) {
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bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
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if (Literal >= -16 && Literal <= 64)
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return true;
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double D = BitsToDouble(Literal);
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if (D == 0.5 || D == -0.5 ||
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D == 1.0 || D == -1.0 ||
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D == 2.0 || D == -2.0 ||
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D == 4.0 || D == -4.0)
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return true;
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if (IsVI && Literal == 0x3fc45f306dc9c882)
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return true;
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return false;
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uint64_t Val = static_cast<uint64_t>(Literal);
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return (Val == DoubleToBits(0.0)) ||
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(Val == DoubleToBits(1.0)) ||
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(Val == DoubleToBits(-1.0)) ||
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(Val == DoubleToBits(0.5)) ||
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(Val == DoubleToBits(-0.5)) ||
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(Val == DoubleToBits(2.0)) ||
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(Val == DoubleToBits(-2.0)) ||
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(Val == DoubleToBits(4.0)) ||
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(Val == DoubleToBits(-4.0)) ||
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(Val == 0x3fc45f306dc9c882 && HasInv2Pi);
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}
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bool isInlinableLiteral32(int32_t Literal, bool IsVI) {
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bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
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if (Literal >= -16 && Literal <= 64)
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return true;
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float F = BitsToFloat(Literal);
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if (F == 0.5 || F == -0.5 ||
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F == 1.0 || F == -1.0 ||
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F == 2.0 || F == -2.0 ||
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F == 4.0 || F == -4.0)
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return true;
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if (IsVI && Literal == 0x3e22f983)
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return true;
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return false;
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uint32_t Val = static_cast<uint32_t>(Literal);
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return (Val == FloatToBits(0.0f)) ||
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(Val == FloatToBits(1.0f)) ||
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(Val == FloatToBits(-1.0f)) ||
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(Val == FloatToBits(0.5f)) ||
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(Val == FloatToBits(-0.5f)) ||
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(Val == FloatToBits(2.0f)) ||
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(Val == FloatToBits(-2.0f)) ||
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(Val == FloatToBits(4.0f)) ||
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(Val == FloatToBits(-4.0f)) ||
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(Val == 0x3e22f983 && HasInv2Pi);
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}
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@ -168,8 +168,12 @@ unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
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unsigned OpNo);
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/// \brief Is this literal inlinable
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bool isInlinableLiteral64(int64_t Literal, bool IsVI);
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bool isInlinableLiteral32(int32_t Literal, bool IsVI);
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LLVM_READNONE
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bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
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LLVM_READNONE
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bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
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} // end namespace AMDGPU
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} // end namespace llvm
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