forked from OSchip/llvm-project
AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR
Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D48196 llvm-svn: 335318
This commit is contained in:
Tom Stellard
parent
fe70b29cf7
commit
26fac0f8e1
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@ -18,6 +18,11 @@ def gi_vsrc0 :
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GIComplexOperandMatcher<s32, "selectVSRC0">,
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GIComplexPatternEquiv<sd_vsrc0>;
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def sd_vcsrc : ComplexPattern<i32, 1, "">;
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def gi_vcsrc :
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GIComplexOperandMatcher<s32, "selectVCSRC">,
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GIComplexPatternEquiv<sd_vcsrc>;
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def gi_vop3mods0 :
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GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
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GIComplexPatternEquiv<VOP3Mods0>;
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@ -60,6 +65,26 @@ class GISelVop2CommutePat <
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(inst src0_vt:$src0, src1_vt:$src1)
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>;
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class GISelVop3Pat2 <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
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(inst src0_vt:$src0, src1_vt:$src1)
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>;
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class GISelVop3Pat2CommutePat <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
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(inst src0_vt:$src1, src1_vt:$src0)
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>;
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multiclass GISelVop2IntrPat <
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SDPatternOperator node, Instruction inst,
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ValueType dst_vt, ValueType src_vt = dst_vt> {
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@ -76,6 +101,15 @@ multiclass GISelVop2IntrPat <
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def : GISelSop2Pat <or, S_OR_B32, i32>;
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def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
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def : GISelSop2Pat <sra, S_ASHR_I32, i32>;
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let AddedComplexity = 100 in {
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let SubtargetPredicate = isSICI in {
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def : GISelVop2Pat <sra, V_ASHR_I32_e32, i32>;
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}
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def : GISelVop2CommutePat <sra, V_ASHRREV_I32_e32, i32>;
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}
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def : GISelVop3Pat2CommutePat <sra, V_ASHRREV_I32_e64, i32>;
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// FIXME: Select directly to _e32 so we don't need to deal with modifiers.
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// FIXME: We can't re-use SelectionDAG patterns here because they match
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// against a custom SDNode and we would need to create a generic machine
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@ -537,6 +537,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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switch (I.getOpcode()) {
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default:
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break;
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case TargetOpcode::G_ASHR:
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case TargetOpcode::G_SITOFP:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FADD:
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@ -564,6 +565,14 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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return false;
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}
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const {
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.add(Root); }
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}};
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}
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///
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/// This will select either an SGPR or VGPR operand and will save us from
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/// having to write an extra tablegen pattern.
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@ -72,6 +72,9 @@ private:
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bool selectG_LOAD(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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InstructionSelector::ComplexRendererFns
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selectVCSRC(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVSRC0(MachineOperand &Root) const;
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@ -55,6 +55,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
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};
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setAction({G_ADD, S32}, Legal);
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setAction({G_ASHR, S32}, Legal);
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setAction({G_SUB, S32}, Legal);
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setAction({G_MUL, S32}, Legal);
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setAction({G_AND, S32}, Legal);
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@ -0,0 +1,86 @@
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,SI
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,VI
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--- |
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define void @ashr(i32 addrspace(1)* %global0) {ret void}
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...
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---
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name: ashr
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legalized: true
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regBankSelected: true
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# GCN-LABEL: name: ashr
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
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; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:vgpr(s32) = COPY $vgpr0
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%3:vgpr(s64) = COPY $vgpr3_vgpr4
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; GCN: [[C1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
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; GCN: [[C4096:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
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%4:sgpr(s32) = G_CONSTANT i32 1
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%5:sgpr(s32) = G_CONSTANT i32 4096
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; ashr ss
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; GCN: [[SS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SGPR0]], [[SGPR1]]
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%6:sgpr(s32) = G_ASHR %0, %1
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; ashr si
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; GCN: [[SI:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SS]], [[C1]]
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%7:sgpr(s32) = G_ASHR %6, %4
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; ashr is
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; GCN: [[IS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[C1]], [[SI]]
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%8:sgpr(s32) = G_ASHR %4, %7
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; ashr sc
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; GCN: [[SC:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[IS]], [[C4096]]
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%9:sgpr(s32) = G_ASHR %8, %5
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; ashr cs
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; GCN: [[CS:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[C4096]], [[SC]]
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%10:sgpr(s32) = G_ASHR %5, %9
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; ashr vs
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; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[CS]], [[VGPR0]]
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%11:vgpr(s32) = G_ASHR %2, %10
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; ashr sv
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; SI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[CS]], [[VS]]
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; VI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VS]], [[CS]]
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%12:vgpr(s32) = G_ASHR %10, %11
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; ashr vv
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; SI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[SV]], [[VGPR0]]
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; VI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[VGPR0]], [[SV]]
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%13:vgpr(s32) = G_ASHR %12, %2
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; ashr iv
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; SI: [[IV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[C1]], [[VV]]
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; VI: [[IV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VV]], [[C1]]
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%14:vgpr(s32) = G_ASHR %4, %13
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; ashr vi
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; GCN: [[VI:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[C1]], [[IV]]
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%15:vgpr(s32) = G_ASHR %14, %4
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; ashr cv
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; SI: [[CV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[C4096]], [[VI]]
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; VI: [[CV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VI]], [[C4096]]
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%16:vgpr(s32) = G_ASHR %5, %15
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; ashr vc
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; GCN: [[VC:%[-1-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[C4096]], [[CV]]
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%17:vgpr(s32) = G_ASHR %16, %5
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G_STORE %17, %3 :: (store 4 into %ir.global0)
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...
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---
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@ -0,0 +1,22 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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---
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name: test_ashr
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0.entry:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_ashr
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]]
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%0(s32) = COPY $vgpr0
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%1(s32) = COPY $vgpr1
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%2(s32) = G_ASHR %0, %1
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$vgpr0 = COPY %2
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...
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