maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU/GlobalISel: Fix smrd loads of v4i64

This commit is contained in:
Matt Arsenault 2020-02-09 16:30:22 -05:00 committed by Matt Arsenault
parent 88b493a838
commit 26ebc51a34
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
View File

@ -578,7 +578,7 @@ def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
let AllocationPriority = 16;
}
def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> {
def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32, (add SGPR_256Regs)> {
let AllocationPriority = 17;
}
@ -586,7 +586,7 @@ def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> {
let isAllocatable = 0;
}
def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32,
(add SGPR_256, TTMP_256)> {
// Requires 4 s_mov_b64 to copy
let CopyCost = 4;

4
llvm/lib/Target/AMDGPU/SMInstructions.td
View File

@ -808,7 +808,9 @@ foreach vt = SReg_128.RegTypes in {
defm : SMRD_Pattern <"S_LOAD_DWORDX4", vt>;
}
defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
foreach vt = SReg_256.RegTypes in {
defm : SMRD_Pattern <"S_LOAD_DWORDX8", vt>;
}
defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORD", i32>;