forked from OSchip/llvm-project
[RISCV] Add the zvl extension according to the v1.0 spec
`zvl` is the new standard vector extension that specifies the minimum vector length of the vector extension. The `zvl` extension is related to the `zve` extension and other updates that are added in v1.0. According to https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21, Clang defines macro `__riscv_v_min_vlen` for `zvl` and it can be used for applications that uses the vector extension. LLVM checks whether the option `riscv-v-vector-bits-min` (if specified) matches the `zvl*` extension specified. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D108694
This commit is contained in:
eopXD
parent
35d00fdc10
commit
26bb1b1dab
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@ -125,6 +125,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
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Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
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StringRef CodeModel = getTargetOpts().CodeModel;
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unsigned FLen = ISAInfo->getFLen();
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unsigned MinVLen = ISAInfo->getMinVLen();
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if (CodeModel == "default")
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CodeModel = "small";
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@ -176,6 +177,9 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
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Builder.defineMacro("__riscv_fsqrt");
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}
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if (MinVLen)
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Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen));
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if (ISAInfo->hasExtension("c"))
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Builder.defineMacro("__riscv_compressed");
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@ -434,3 +434,17 @@
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// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
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// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
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// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"
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// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -### %s -c 2>&1 | \
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// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
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// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izvl32b0p10'
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// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions'
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// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
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// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s
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// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izvl32b0p1'
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// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension
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// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
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// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s
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// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b"
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@ -243,3 +243,53 @@
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// RUN: -march=rv64izfh1p0 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
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// CHECK-ZFH-EXT: __riscv_zfh 10000
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s
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// CHECK-V-MINVLEN: __riscv_v_min_vlen 128
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl256b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL256b %s
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// CHECK-ZVL256b: __riscv_v_min_vlen 256
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl512b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL512b %s
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// CHECK-ZVL512b: __riscv_v_min_vlen 512
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl1024b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL1024b %s
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// CHECK-ZVL1024b: __riscv_v_min_vlen 1024
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl2048b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL2048b %s
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// CHECK-ZVL2048b: __riscv_v_min_vlen 2048
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl4096b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL4096b %s
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// CHECK-ZVL4096b: __riscv_v_min_vlen 4096
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl8192b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL8192b %s
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// CHECK-ZVL8192b: __riscv_v_min_vlen 8192
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl16384b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL16384b %s
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// CHECK-ZVL16384b: __riscv_v_min_vlen 16384
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl32768b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL32768b %s
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// CHECK-ZVL32768b: __riscv_v_min_vlen 32768
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// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
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// RUN: -march=rv64iv0p10_zvl65536b0p10 -x c -E -dM %s -o - \
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// RUN: | FileCheck --check-prefix=CHECK-ZVL65536b %s
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// CHECK-ZVL65536b: __riscv_v_min_vlen 65536
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@ -61,6 +61,7 @@ public:
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unsigned getXLen() const { return XLen; };
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unsigned getFLen() const { return FLen; };
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unsigned getMinVLen() const { return MinVLen; }
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bool hasExtension(StringRef Ext) const;
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std::string toString() const;
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@ -71,10 +72,11 @@ public:
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unsigned MinorVersion);
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private:
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RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0) {}
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RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0), MinVLen(0) {}
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unsigned XLen;
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unsigned FLen;
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unsigned MinVLen;
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OrderedExtensionMap Exts;
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@ -85,6 +87,7 @@ private:
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void updateImplication();
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void updateFLen();
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void updateMinVLen();
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};
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} // namespace llvm
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@ -9,6 +9,7 @@
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#include "llvm/Support/RISCVISAInfo.h"
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#include "llvm/ADT/None.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/Errc.h"
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@ -66,6 +67,18 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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{"zbt", RISCVExtensionVersion{0, 93}},
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{"zvlsseg", RISCVExtensionVersion{0, 10}},
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{"zvl32b", RISCVExtensionVersion{0, 10}},
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{"zvl64b", RISCVExtensionVersion{0, 10}},
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{"zvl128b", RISCVExtensionVersion{0, 10}},
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{"zvl256b", RISCVExtensionVersion{0, 10}},
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{"zvl512b", RISCVExtensionVersion{0, 10}},
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{"zvl1024b", RISCVExtensionVersion{0, 10}},
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{"zvl2048b", RISCVExtensionVersion{0, 10}},
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{"zvl4096b", RISCVExtensionVersion{0, 10}},
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{"zvl8192b", RISCVExtensionVersion{0, 10}},
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{"zvl16384b", RISCVExtensionVersion{0, 10}},
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{"zvl32768b", RISCVExtensionVersion{0, 10}},
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{"zvl65536b", RISCVExtensionVersion{0, 10}},
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};
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static bool stripExperimentalPrefix(StringRef &Ext) {
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@ -435,6 +448,7 @@ RISCVISAInfo::parseFeatures(unsigned XLen,
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ISAInfo->updateImplication();
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ISAInfo->updateFLen();
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ISAInfo->updateMinVLen();
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if (Error Result = ISAInfo->checkDependency())
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return std::move(Result);
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@ -658,6 +672,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
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ISAInfo->updateImplication();
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ISAInfo->updateFLen();
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ISAInfo->updateMinVLen();
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if (Error Result = ISAInfo->checkDependency())
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return std::move(Result);
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@ -691,8 +706,19 @@ Error RISCVISAInfo::checkDependency() {
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return Error::success();
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}
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static const char *ImpliedExtsV[] = {"zvlsseg"};
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static const char *ImpliedExtsV[] = {"zvlsseg", "zvl128b"};
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static const char *ImpliedExtsZfh[] = {"zfhmin"};
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static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
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static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
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static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};
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static const char *ImpliedExtsZvl8192b[] = {"zvl4096b"};
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static const char *ImpliedExtsZvl4096b[] = {"zvl2048b"};
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static const char *ImpliedExtsZvl2048b[] = {"zvl1024b"};
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static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
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static const char *ImpliedExtsZvl512b[] = {"zvl256b"};
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static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
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static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
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static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
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struct ImpliedExtsEntry {
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StringLiteral Name;
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@ -708,6 +734,17 @@ struct ImpliedExtsEntry {
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static constexpr ImpliedExtsEntry ImpliedExts[] = {
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{{"v"}, {ImpliedExtsV}},
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{{"zfh"}, {ImpliedExtsZfh}},
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{{"zvl1024b"}, {ImpliedExtsZvl1024b}},
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{{"zvl128b"}, {ImpliedExtsZvl128b}},
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{{"zvl16384b"}, {ImpliedExtsZvl16384b}},
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{{"zvl2048b"}, {ImpliedExtsZvl2048b}},
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{{"zvl256b"}, {ImpliedExtsZvl256b}},
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{{"zvl32768b"}, {ImpliedExtsZvl32768b}},
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{{"zvl4096b"}, {ImpliedExtsZvl4096b}},
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{{"zvl512b"}, {ImpliedExtsZvl512b}},
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{{"zvl64b"}, {ImpliedExtsZvl64b}},
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{{"zvl65536b"}, {ImpliedExtsZvl65536b}},
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{{"zvl8192b"}, {ImpliedExtsZvl8192b}},
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};
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void RISCVISAInfo::updateImplication() {
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@ -722,12 +759,25 @@ void RISCVISAInfo::updateImplication() {
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}
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assert(llvm::is_sorted(ImpliedExts) && "Table not sorted by Name");
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for (auto &Ext : Exts) {
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auto I = llvm::lower_bound(ImpliedExts, Ext.first);
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if (I != std::end(ImpliedExts) && I->Name == Ext.first) {
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for (auto &ImpliedExt : I->Exts) {
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// This loop may execute over 1 iteration since implication can be layered
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// Exits loop if no more implication is applied
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SmallSetVector<StringRef, 16> WorkList;
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for (auto &Ext : Exts)
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WorkList.insert(Ext.first);
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while (!WorkList.empty()) {
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StringRef ExtName = WorkList.pop_back_val();
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auto I = llvm::lower_bound(ImpliedExts, ExtName);
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if (I != std::end(ImpliedExts) && I->Name == ExtName) {
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for (const char *ImpliedExt : I->Exts) {
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if (WorkList.count(ImpliedExt))
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continue;
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if (Exts.count(ImpliedExt))
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continue;
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auto Version = findDefaultVersion(ImpliedExt);
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addExtension(ImpliedExt, Version->Major, Version->Minor);
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WorkList.insert(ImpliedExt);
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}
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}
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}
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@ -742,6 +792,18 @@ void RISCVISAInfo::updateFLen() {
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FLen = 32;
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}
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void RISCVISAInfo::updateMinVLen() {
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for (auto Ext : Exts) {
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StringRef ExtName = Ext.first;
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bool IsZvlExt = ExtName.consume_front("zvl") && ExtName.consume_back("b");
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if (IsZvlExt) {
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unsigned ZvlLen;
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if (!ExtName.getAsInteger(10, ZvlLen))
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MinVLen = std::max(MinVLen, ZvlLen);
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}
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}
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}
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std::string RISCVISAInfo::toString() const {
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std::string Buffer;
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raw_string_ostream Arch(Buffer);
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@ -150,9 +150,21 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
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AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
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"RVC Hint Instructions">;
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def FeatureStdExtZvl32b : SubtargetFeature<"experimental-zvl32b", "ZvlLen", "ExtZvl::Zvl32b",
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"'Zvl' (Minimum Vector Length) 32">;
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foreach i = { 6-15 } in {
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defvar I = !shl(1, i);
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def FeatureStdExtZvl#I#b :
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SubtargetFeature<"experimental-zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b",
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"'Zvl' (Minimum Vector Length) "#I,
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[!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
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}
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def FeatureStdExtV
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: SubtargetFeature<"experimental-v", "HasStdExtV", "true",
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"'V' (Vector Instructions)">;
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"'V' (Vector Instructions)",
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[FeatureStdExtZvl128b]>;
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def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
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AssemblerPredicate<(all_of FeatureStdExtV),
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"'V' (Vector Instructions)">;
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@ -18,6 +18,7 @@
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#include "RISCVRegisterBankInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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@ -140,7 +141,15 @@ unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
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"Tried to get vector length without Zve or V extension support!");
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if (RVVVectorBitsMax == 0)
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return 0;
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assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
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// ZvlLen specifies the minimum required vlen. The upper bound provided by
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// riscv-v-vector-bits-max should be no less than it.
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if (RVVVectorBitsMax < ZvlLen)
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report_fatal_error("riscv-v-vector-bits-max specified is lower "
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"than the Zvl*b limitation");
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// FIXME: Change to >= 32 when VLEN = 32 is supported
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assert(RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
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isPowerOf2_32(RVVVectorBitsMax) &&
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"V extension requires vector length to be in the range of 128 to "
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"65536 and a power of 2!");
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@ -152,10 +161,17 @@ unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
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}
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unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
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// ZvlLen specifies the minimum required vlen. The lower bound provided by
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// riscv-v-vector-bits-min should be no less than it.
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if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
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report_fatal_error("riscv-v-vector-bits-min specified is lower "
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"than the Zvl*b limitation");
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assert(hasVInstructions() &&
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"Tried to get vector length without Zve or V extension support!");
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// FIXME: Change to >= 32 when VLEN = 32 is supported
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assert((RVVVectorBitsMin == 0 ||
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(RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
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(RVVVectorBitsMin >= 64 && RVVVectorBitsMax <= 65536 &&
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isPowerOf2_32(RVVVectorBitsMin))) &&
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"V extension requires vector length to be in the range of 128 to "
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"65536 and a power of 2!");
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@ -34,6 +34,22 @@ class StringRef;
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class RISCVSubtarget : public RISCVGenSubtargetInfo {
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public:
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enum ExtZvl : unsigned {
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NotSet = 0,
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Zvl32b = 32,
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Zvl64b = 64,
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Zvl128b = 128,
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Zvl256b = 256,
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Zvl512b = 512,
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Zvl1024b = 1024,
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Zvl2048b = 2048,
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Zvl4096b = 4096,
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Zvl8192b = 8192,
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Zvl16384b = 16384,
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Zvl32768b = 32768,
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Zvl65536b = 65536
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};
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enum RISCVProcFamilyEnum : uint8_t {
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Others,
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SiFive7,
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@ -69,6 +85,7 @@ private:
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bool EnableRVCHintInstrs = true;
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bool EnableSaveRestore = false;
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unsigned XLen = 32;
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ExtZvl ZvlLen = ExtZvl::NotSet;
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MVT XLenVT = MVT::i32;
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uint8_t MaxInterleaveFactor = 2;
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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@ -134,6 +151,7 @@ public:
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bool hasStdExtZbt() const { return HasStdExtZbt; }
|
||||
bool hasStdExtV() const { return HasStdExtV; }
|
||||
bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
|
||||
bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
|
||||
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
|
||||
bool hasStdExtZfh() const { return HasStdExtZfh; }
|
||||
bool is64Bit() const { return HasRV64; }
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
; RV32F: .attribute 5, "rv32i2p0_f2p0"
|
||||
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
|
||||
; RV32C: .attribute 5, "rv32i2p0_c2p0"
|
||||
; RV32V: .attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
|
||||
; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
|
||||
; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
|
||||
; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
|
||||
|
|
@ -53,7 +53,7 @@
|
|||
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
|
||||
; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
|
||||
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
|
||||
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvlsseg0p10"
|
||||
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
; RV64M: .attribute 5, "rv64i2p0_m2p0"
|
||||
; RV64A: .attribute 5, "rv64i2p0_a2p0"
|
||||
|
|
@ -72,8 +72,8 @@
|
|||
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
|
||||
; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
|
||||
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
|
||||
; RV64V: .attribute 5, "rv64i2p0_v0p10_zvlsseg0p10"
|
||||
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvlsseg0p10"
|
||||
; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
|
||||
define i32 @addi(i32 %a) {
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
## Experimental extensions require version string to be explicitly specified
|
||||
|
||||
.attribute arch, "rv32iv0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32izba1p0"
|
||||
# CHECK: attribute 5, "rv32i2p0_zba1p0"
|
||||
|
|
@ -74,5 +74,41 @@
|
|||
.attribute arch, "rv32ifzfh1p0"
|
||||
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvlsseg0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
|
||||
.attribute arch, "rv32iv0p10_zvlsseg0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl32b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl64b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl128b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl256b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl512b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl1024b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl2048b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl4096b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl8192b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl16384b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl32768b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
|
||||
|
||||
.attribute arch, "rv32iv0p10zvl65536b0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
|
||||
|
|
|
|||
Loading…
Reference in New Issue