forked from OSchip/llvm-project
parent
59c23cd946
commit
26b808922b
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@ -956,6 +956,26 @@ public:
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llvm_unreachable("Store conditional unimplemented on this target");
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}
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/// Inserts in the IR a target-specific intrinsic specifying a fence.
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/// It is called by AtomicExpandPass before expanding an
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/// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
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/// RMW and CmpXchg set both IsStore and IsLoad to true.
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/// Backends with !getInsertFencesForAtomic() should keep a no-op here
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virtual void emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
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bool IsStore, bool IsLoad) const {
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assert(!getInsertFencesForAtomic());
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}
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/// Inserts in the IR a target-specific intrinsic specifying a fence.
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/// It is called by AtomicExpandPass after expanding an
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/// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
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/// RMW and CmpXchg set both IsStore and IsLoad to true.
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/// Backends with !getInsertFencesForAtomic() should keep a no-op here
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virtual void emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
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bool IsStore, bool IsLoad) const {
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assert(!getInsertFencesForAtomic());
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}
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/// Return true if the given (atomic) instruction should be expanded by the
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/// IR-level AtomicExpand pass into a loop involving
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/// load-linked/store-conditional pairs. Atomic stores will be expanded in the
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