forked from OSchip/llvm-project
[X86] Various vXi1 insertion improvements.
Add missing patterns for inserting v1i1 into a zero vector. Use insert_subvector to zero upper bits before inserting an element into a vXi1 vector. Replace kshift based isel pattern with insert_subvector based pattern now that code that caused the pattern has been fixed to emit insert_subvector. llvm-svn: 323173
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@ -14922,10 +14922,10 @@ static SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG,
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// Insertion of one bit into first position
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if (IdxVal == 0) {
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// Clean top bits of vector.
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EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec,
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DAG.getConstant(NumElems - 1, dl, MVT::i8));
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EltInVec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, EltInVec,
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DAG.getConstant(NumElems - 1, dl, MVT::i8));
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EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Elt);
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EltInVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT,
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getZeroVector(VecVT, Subtarget, DAG, dl),
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EltInVec, DAG.getIntPtrConstant(0, dl));
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// Clean the first bit in source vector.
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Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,
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DAG.getConstant(1 , dl, MVT::i8));
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@ -2761,19 +2761,12 @@ let Predicates = [HasAVX512] in {
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defm : operation_gpr_mask_copy_lowering<VK32, v32i1>;
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defm : operation_gpr_mask_copy_lowering<VK64, v64i1>;
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def : Pat<(X86kshiftr (X86kshiftl (v1i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
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def : Pat<(insert_subvector (v16i1 immAllZerosV),
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(v1i1 (scalar_to_vector GR8:$src)), (iPTR 0)),
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(COPY_TO_REGCLASS
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(KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
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GR8:$src, sub_8bit), (i32 1))), VK1)>;
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def : Pat<(X86kshiftr (X86kshiftl (v16i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
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(COPY_TO_REGCLASS
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(KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
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GR8:$src, sub_8bit), (i32 1))), VK16)>;
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def : Pat<(X86kshiftr (X86kshiftl (v8i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
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(COPY_TO_REGCLASS
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(KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
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GR8:$src, sub_8bit), (i32 1))), VK8)>;
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(KMOVWkr (AND32ri8
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(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit),
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(i32 1))), VK16)>;
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}
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// Mask unary operation
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@ -496,6 +496,11 @@ let Predicates = [HasBWI, HasVLX] in {
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// If the bits are not zero we have to fall back to explicitly zeroing by
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// using shifts.
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let Predicates = [HasAVX512] in {
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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(v1i1 VK1:$mask), (iPTR 0))),
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(KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16),
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(i8 15)), (i8 15))>;
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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(v2i1 VK2:$mask), (iPTR 0))),
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(KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16),
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@ -519,6 +524,10 @@ let Predicates = [HasDQI] in {
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(v8i1 VK8:$mask), (iPTR 0))),
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(COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>;
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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(v1i1 VK1:$mask), (iPTR 0))),
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(KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8),
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(i8 7)), (i8 7))>;
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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(v2i1 VK2:$mask), (iPTR 0))),
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(KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8),
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@ -565,6 +574,10 @@ let Predicates = [HasBWI, HasDQI] in {
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}
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let Predicates = [HasBWI, HasVLX] in {
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def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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(v1i1 VK1:$mask), (iPTR 0))),
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(KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32),
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(i8 31)), (i8 31))>;
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def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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(v2i1 VK2:$mask), (iPTR 0))),
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(KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32),
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@ -574,6 +587,10 @@ let Predicates = [HasBWI, HasVLX] in {
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(KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK4:$mask, VK32),
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(i8 28)), (i8 28))>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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(v1i1 VK1:$mask), (iPTR 0))),
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(KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64),
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(i8 63)), (i8 63))>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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(v2i1 VK2:$mask), (iPTR 0))),
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(KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64),
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