diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 7760339662d3..c1a85096157d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1301,7 +1301,7 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
              I != E; ++I) {
           if (I->isCtrl) continue;
           SUnit *SuccSU = I->Dep;
-          // Don't constraint nodes with implicit defs. It can create cycles
+          // Don't constrain nodes with implicit defs. It can create cycles
           // plus it may increase register pressures.
           if (SuccSU == SU || SuccSU->hasPhysRegDefs)
             continue;